Patents by Inventor You-Lung Yen
You-Lung Yen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11574856Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.Type: GrantFiled: April 2, 2021Date of Patent: February 7, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Bernd Karl Appelt, You-Lung Yen, Kay Stefan Essig
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Publication number: 20230037201Abstract: A electronic package and a method of manufacturing the same are provided. The electronic package includes an electronic component, a thermal spreading element, and an encapsulant. The electronic component has a first surface. The thermal spreading element is disposed over the electronic component and has a first surface facing the first surface of the electronic component. The encapsulant covers the electronic component and has a first surface closer to the first surface of the thermal spreading element than the first surface of the electronic component.Type: ApplicationFiled: July 30, 2021Publication date: February 2, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl Appelt
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Patent number: 11545406Abstract: A substrate structure, a semiconductor package structure including the same and a method for manufacturing the same are provided. The substrate structure includes a first passivation layer, a first circuit layer and a first protection layer. The first passivation layer has a first surface and a second surface opposite to the first surface. The first circuit layer has an outer lateral surface. A first portion of the first circuit layer is disposed in the first passivation layer. The first protection layer is disposed on a second portion of the first circuit layer and exposed from the first surface of the first passivation layer. The outer lateral surface of the first circuit layer is covered by the first passivation layer or the first protection layer.Type: GrantFiled: October 8, 2020Date of Patent: January 3, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stefan Essig
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Publication number: 20220367384Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate, a semiconductor device, an encapsulant, a balance structure, and a warpage-resistant layer. The semiconductor device is disposed on the substrate. The encapsulant encapsulates the semiconductor device. The balance structure is on the semiconductor device and contacting the encapsulant. The warpage-resistant layer is between the semiconductor device and the balance structure. The encapsulant contacts a lateral surface of the warpage-resistant layer.Type: ApplicationFiled: May 14, 2021Publication date: November 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
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Publication number: 20220359363Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first package and a second package. The first package includes a first substrate, an electronic component, a trace layer, and a first conductive structure. The first substrate has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the first substrate. The trace layer has an uppermost conductive layer embedded in the first substrate and exposed from the first surface of the first substrate. The first conductive structure electrically connects the trace layer to the second surface of the first substrate. The second package is disposed on the first surface of the first substrate of the first package.Type: ApplicationFiled: May 7, 2021Publication date: November 10, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
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Publication number: 20220359361Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.Type: ApplicationFiled: July 25, 2022Publication date: November 10, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chun-Che LEE, Ming-Chiang LEE, Yuan-Chang SU, Tien-Szu CHEN, Chih-Cheng LEE, You-Lung YEN
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Patent number: 11482480Abstract: A package substrate and method of manufacturing a package substrate and a semiconductor device package are provided. The package substrate includes a circuit layer, an optically-cured dielectric layer, a plurality of block layers and a sacrificial layer. The circuit layer includes a plurality of conductive pads. The optically-cured dielectric layer has an upper surface and a lower surface opposite to the upper surface. The optically-cured dielectric layer covers the circuit layer, and first surfaces of the conductive pads are at least partially exposed from the upper surface of the optically-cured dielectric layer. The block layers are respectively disposed on the first surfaces of the conductive pads exposed by the optically-cured dielectric layer. The sacrificial layer is disposed on the optically-cured dielectric layer and covering the block layers.Type: GrantFiled: March 19, 2020Date of Patent: October 25, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventor: You-Lung Yen
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Publication number: 20220336332Abstract: A conductive structure, a package structure and a method for manufacturing the same are provided. The conductive structure includes a main portion, a first electrical contact, a second electrical contact, a first post and a second post. The main portion has a first surface and a second surface opposite to the first surface. The first electrical contact is disposed adjacent to the first surface of the main portion. The second electrical contact is disposed adjacent to the second surface of the main portion and electrically connected to the first electrical contact. The first post is electrically connected to the first electrical contact. The second post is electrically connected to the second electrical contact.Type: ApplicationFiled: April 16, 2021Publication date: October 20, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Publication number: 20220328416Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a substrate and a first passive device. The substrate has a first surface and a second surface opposite to the first surface. The first passive device includes a first terminal and a second terminal, wherein the first terminal is closer to the first surface than to the second surface, and the second terminal is closer to the second surface than to the first surface.Type: ApplicationFiled: April 8, 2021Publication date: October 13, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stefan ESSIG
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Publication number: 20220319972Abstract: A semiconductor device package and method for manufacturing the same are provided. The semiconductor device package includes a dielectric layer, an electronic component, a first conductive layer, and a conductive element. The dielectric layer has a first surface and a second surface opposite to the first surface. The electronic component is embedded in the dielectric layer. The first conductive layer is embedded in the dielectric layer and adjacent to the first surface of the dielectric layer. The conductive element is disposed on the first surface of the dielectric layer and in contact with the first conductive layer.Type: ApplicationFiled: April 6, 2021Publication date: October 6, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Patent number: 11462484Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.Type: GrantFiled: October 8, 2020Date of Patent: October 4, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt, Kay Stephan Essig
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Publication number: 20220310410Abstract: A substrate structure, a package structure, and a method for manufacturing an electronic package structure provided. The substrate structure includes a dielectric layer, a trace layer, and at least one wettable flank. The dielectric layer has a first surface and a second surface opposite to the first surface. The trace layer is embedded in the dielectric layer and exposed from the first surface of the dielectric layer. The at least one wettable flank is stacked with a portion of the trace layer embedded in the dielectric layer.Type: ApplicationFiled: March 25, 2021Publication date: September 29, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Publication number: 20220302008Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate, a first module disposed on the substrate, a second module disposed on the substrate and spaced apart from the first module, and a conductive element disposed outside of the substrate and configured to provide a signal transmission path between the first module and the second module.Type: ApplicationFiled: March 22, 2021Publication date: September 22, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Publication number: 20220301989Abstract: A substrate structure and a semiconductor package structure including the same are provided. The substrate structure includes a circuit layer and a dielectric structure. The circuit layer has a bottom surface and a top surface opposite to the bottom surface. The dielectric structure around the circuit layer. The dielectric structure covers a first part of the bottom surface of the circuit layer, and exposes a second part of the bottom surface and the top surface of the circuit layer. The dielectric structure exposes the top surface of the circuit layer. In addition, a method of manufacturing a semiconductor package structure is also provided.Type: ApplicationFiled: March 17, 2021Publication date: September 22, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Kuang-Hsiung CHEN, Bernd Karl APPELT
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Publication number: 20220302004Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a substrate having a first surface and a second surface opposite to the first surface of the substrate. The substrate has a through opening extending between the first surface of the substrate and the second surface of the substrate. The semiconductor device package also includes a conductive pad in the through opening and approximal to the second surface of the substrate. The conductive pad has a first surface and a second surface opposite to the first surface of the conductive pad. The semiconductor device package also includes a conductive pillar in contact with the first surface of the conductive pad. The second surface of the conductive pad protrudes from the second surface of the substrate. A method of manufacturing a semiconductor device package is also disclosed.Type: ApplicationFiled: March 18, 2021Publication date: September 22, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT
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Patent number: 11398421Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.Type: GrantFiled: January 14, 2019Date of Patent: July 26, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chun-Che Lee, Ming-Chiang Lee, Yuan-Chang Su, Tien-Szu Chen, Chih-Cheng Lee, You-Lung Yen
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Patent number: 11322428Abstract: A semiconductor device package includes a substrate, a first semiconductor die, a conductive via, a first contact pad and a second contact pad. The substrate includes a first surface, and a second surface opposite to the first surface, the substrate defines a cavity through the substrate. The first semiconductor die is disposed in the cavity, wherein the first semiconductor die includes an active surface adjacent to the first surface, and an inactive surface. The conductive via penetrates through the substrate. The first contact pad is exposed from the active surface of the first semiconductor die and adjacent to the first surface of the substrate. The second contact pad is disposed on the first surface of the substrate, wherein the second contact pad is connected to a first end of the conductive via.Type: GrantFiled: December 2, 2019Date of Patent: May 3, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 11322468Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate and a metal holder. The substrate includes at least one bonding pad disposed adjacent to its surface and the metal holder is disposed adjacent to the bonding pad.Type: GrantFiled: April 28, 2020Date of Patent: May 3, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Patent number: 11322454Abstract: A semiconductor device package includes an electronic component, an infrared blocking layer, an upper protection layer and a side protection layer. The infrared blocking layer includes a first portion disposed over the electronic component. The infrared blocking layer includes a second portion surrounding the electronic component. The first portion is integral with the second portion. The upper protection layer is disposed on the first portion of the infrared blocking layer. The side protection layer is disposed on the second portion of the infrared blocking layer. The upper protection layer and the side protection layer are formed of different materials.Type: GrantFiled: December 17, 2019Date of Patent: May 3, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: You-Lung Yen, Bernd Karl Appelt
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Publication number: 20220115328Abstract: An electronic package and manufacturing method thereof are provided. The electronic package includes a substrate, a first encapsulant, a wettable flank and a shielding layer. The substrate includes a first surface, a second surface opposite to the first surface and a side surface connecting the first surface and the second surface. The first encapsulant is disposed on the first surface of the substrate. The wettable flank is exposed from the side surface of the substrate. The shielding layer covers a side surface of the first encapsulant, wherein on the side surface of the substrate, the shielding layer is spaced apart from the wettable flank.Type: ApplicationFiled: October 8, 2020Publication date: April 14, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: You-Lung YEN, Bernd Karl APPELT, Kay Stephan ESSIG