Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.

Abstract: A semiconductor package structure includes a patterned conductive layer with a front surface, a back surface, and a side surface connecting the front surface and the back surface. The semiconductor package structure further includes a first semiconductor chip on the front surface and electrically connected to the patterned conductive layer, a first encapsulant covering at least the back surface of the patterned conductive layer, and a second encapsulant covering at least the front surface of the patterned conductive layer, the side surface being covered by one of the first encapsulant and the second encapsulant.

Abstract: A semiconductor package includes a base material, a capture land, an interconnection structure, a semiconductor chip and an encapsulant. The base material has a top surface and an inner lateral surface. The capture land is disposed in or on the base material, and has an outer side surface. The interconnection structure is disposed along the inner lateral surface of the base material, and on the capture land. The interconnection structure has an outer side surface. An outer side surface of the semiconductor package includes the outer side surface of the capture land and the outer side surface of the interconnection structure. The semiconductor chip is disposed on the top surface of the base material. The encapsulant is disposed adjacent to the top surface of the base material, and covers the semiconductor chip.

Abstract: A semiconductor package structure includes a first patterned conductive layer including a first conductive pad, a second conductive pad and a first conductive trace disposed between the first conductive pad and the second first conductive pad. The first conductive pad defines a recess. The semiconductor package structure further includes a second patterned conductive layer including a third conductive pad. The semiconductor package structure further includes a first stud bump electrically connecting the first conductive pad of the first patterned conductive layer to the third conductive pad of the second patterned conductive layer. The semiconductor package structure further includes a first encapsulation layer disposed between the first patterned conductive layer and the second patterned conductive layer.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: A semiconductor package includes a die and a patterned conductive layer electrically connected to the die. The patterned conductive layer includes a connection pad and a trace. The semiconductor package further includes an encapsulation layer encapsulating the die and the patterned conductive layer. The semiconductor package further includes an electrical connection element disposed on the connection pad and a protection layer including a sidewall portion surrounding the electrical connection element.

Abstract: A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive layer. The first encapsulant encloses the first semiconductor die and has a top surface and a lateral surface. The first redistribution layer is disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant. The second encapsulant covers the first encapsulant and the first redistribution layer. The patterned conductive layer is disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, and is electrically connected to the first redistribution layer.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

Abstract: A semiconductor package includes a first semiconductor die, a first encapsulant, a first redistribution layer, a second encapsulant and a patterned conductive layer. The first encapsulant encloses the first semiconductor die and has a top surface and a lateral surface. The first redistribution layer is disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant. The second encapsulant covers the first encapsulant and the first redistribution layer. The patterned conductive layer is disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, and is electrically connected to the first redistribution layer.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.

Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.