Patents by Inventor Youichi Hidaka
Youichi Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9088547Abstract: A VPN connection method and a communication system are provided, each which can omit the setting of a firewall and the installation of a relay server and can establish communications from the outside of a firewall to the inside thereof. The internal network 2 is connected to the external network 1 via the firewall 13. The internal network 2 enables communications by an e-mail from the external network 1 (outside the firewall) to the mail server 21 in the internal network 2 (inside the firewall) or communications by telephone or radio, which is not via the firewall 3. The feature of the firewall 3 is utilized that access from the outside to the inside of the firewall through VPN connection is very difficult but the access in the reverse stream can be simply performed. Using the mail server, telephone line or radio line, the internal network 2 receives an e-mail, which requires for VPN connection from the external network 1, or control information through the telephone line.Type: GrantFiled: July 26, 2005Date of Patent: July 21, 2015Assignee: NEC CORPORATIONInventors: Nobuyuki Enomoto, Youichi Hidaka, Hideo Yoshimi, Atsushi Iwata, Akira Arutaki
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Patent number: 9088432Abstract: In a switching node, a low-load and high-speed control is performed without using a CPU and a network protocol, such as TCP/IP, which have been conventionally used for control from a remote control server, to realize a high-end and high-speed network service by making use of the high-speed CPU processing capacity of a remote control server. Specifically, a forwarding engine incorporates a PCI express, a PCI express LAN conversion bridge and a circuit which can access to a local bus control interface from the PCI express on the switching node. The external control server incorporates an extended network service interface driver for managing a plurality of switching nodes.Type: GrantFiled: February 18, 2011Date of Patent: July 21, 2015Assignee: NEC CorporationInventor: Youichi Hidaka
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Patent number: 9047416Abstract: In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express.Type: GrantFiled: February 18, 2011Date of Patent: June 2, 2015Assignee: NEC CORPORATIONInventors: Youichi Hidaka, Masashi Hayashi, Shihomi Sato, Tsugio Okamoto, Takashi Yokota, Masanori Takashima, Koichi Tsuchiya, Minaxay Philavong, Tetsu Izawa
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Publication number: 20150095518Abstract: An I/O device sharing system characterized by comprising: an I/O device (50) shared by a plurality of hosts (20-1 to 20-N); a system manager (10) which sets the I/O device (50); a virtual bridge (40) which virtualizes the I/O device (50); and a network (3) which connects the I/O device (50), the system manager (10), the plurality of hosts (20-1 to 20-N) and the virtual bridge (40) to each other, wherein the virtual bridge (40) includes a connection virtualization unit (41) by which it is detected that an address setting of a plurality of virtual functions provided in the I/O device (50) that is set by the system manager (10) is performed, the virtual function is enabled, or both of them are performed and each host is permitted to access each virtual function.Type: ApplicationFiled: April 3, 2013Publication date: April 2, 2015Inventors: Jun Suzuki, Youichi Hidaka, Masato Yasuda, Takashi Yoshikawa, Junichi Higuchi
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Publication number: 20140379994Abstract: A local-memory side data transfer unit increments the number of addresses, reads out data from a local memory, and stores the data into a cache memory of a remote-memory side data transfer unit. For preventing data mismatching with the local memory from being stored into the cache memory, a cache clearing operation is executed in units of an elapse of a round trip time period for data transfer between the local memory and the remote memory. Alternatively, the cache clearing operation is executed upon receipt of a signal notifying data transfer of data stored at a specified address.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Applicant: NEC CORPORATIONInventors: Takashi YOSHIKAWA, Jun Suzuki, Youichi Hidaka, Junichi Higuchi, Atsushi Iwata
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Patent number: 8868814Abstract: Fault tolerance is improved, a functional limitation at the time of start-up of an I/O system is avoided, and a start-up time is shortened. A downstream PCI Express bridge sets a PCI Express device connected to the downstream PCI Express bridge itself, among a plurality of single root-compatible PCI Express devices shared by a plurality of root complexes connected to a plurality of upstream PCI Express bridges that exchange data with the downstream PC Express bridge itself through a network, controls and monitors a state of a physical link with the PCI Express device connected to the downstream PCI Express bridge itself, and performs monitoring and notification of an error of the PCI Express device connected to the downstream PCI Express bridge itself.Type: GrantFiled: June 11, 2010Date of Patent: October 21, 2014Assignee: NEC CorporationInventors: Junichi Higuchi, Youichi Hidaka, Jun Suzuki, Takashi Yoshikawa
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Publication number: 20140281053Abstract: A plurality of bridge units which connect a computer, a data movement source I/O device, and a data movement destination I/O device to a network, a memory unit which relays movement of data between the data movement source I/O device and the data movement destination I/O device outside the computer, and an I/O data movement control unit which causes the data movement source I/O device to write data to the memory unit and causes the data movement destination I/O device to read the data from the memory unit are included.Type: ApplicationFiled: October 26, 2012Publication date: September 18, 2014Inventors: Jun Suzuki, Youichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Teruyuki Baba, Yoshikazu Watanabe
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Publication number: 20140245053Abstract: A local computer (20) and a remote I/O device (30) are interconnected on a network (40) through an upstream side bridge (21) and a downstream side bridge (31). The upstream side bridge (21) and the downstream side bridge (31) each include a register (216, 316) for referring to or writing a signal aside from a primary data stream that runs through the network (40) from both sides, and a mechanism (217, 317) for transmitting and receiving the signal aside from the primary data stream inband when referring to or writing the signal in the register (216, 316).Type: ApplicationFiled: June 13, 2012Publication date: August 28, 2014Applicant: NEC CORPORATIONInventors: Takashi Yoshikawa, Youichi Hidaka, Jun Suzuki, Junichi Higuchi
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Patent number: 8775712Abstract: A detecting unit detects a connection of an external device to a connection port and stores the connection in a bridge state storage unit. This setting is autonomously completed by a device before an initial configuration is started by a host. A data transfer unit receives initial configuration data of a link-connection bridge from the host. Data is transferred to the linked-uplink-connection bridge with reference to the bridge state storage unit, data to a bridge which is not linked up is wasted, or an Unsupported Request is returned to the host to represent the absence of the link-connection bridge.Type: GrantFiled: April 7, 2008Date of Patent: July 8, 2014Assignee: NEC CorporationInventors: Jun Suzuki, Youichi Hidaka, Takashi Yoshikawa
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Patent number: 8719483Abstract: Provided is an MRA (multi-root aware) PCI express switch accommodating a plurality of root complexes. The MRA PCI express switch includes: a setting register storing necessary information to set a PCI tree based on a switch connection topology and a physical connection state; and a virtual switch bridge controller storing necessary information to establish a virtual PCI tree, irrespective of a status of the setting register. The root complexes can be booted based on the information in the virtual switch bridge controller.Type: GrantFiled: October 14, 2009Date of Patent: May 6, 2014Assignee: NEC CorporationInventor: Youichi Hidaka
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Patent number: 8683110Abstract: Virtual Functions (VFs) 602-1 to 602-N of an I/O device are separately allocated to a plurality of computers 1-1 to 1-N. In an address swap table 506, a root domain that is an address space of the computer 1 and mapping information of an I/O domain that is an address space unique to the I/O device 6 are registered. Mapping is set with the VFs 602-1 to 602-N as units. When accessing the VFs 602-1 to 602-N of the I/O device 6 to which each of the computers 1-1 to 1-N is allocated, an I/O packet transfer unit 701 checks the address swap table 506 to swap source/destination addresses recorded in packet headers.Type: GrantFiled: August 25, 2008Date of Patent: March 25, 2014Assignee: NEC CorporationInventors: Jun Suzuki, Youichi Hidaka, Takashi Yoshikawa
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Publication number: 20140059250Abstract: A network system of the present invention includes a computer and a device connected via a network, and a system management device. The computer and the device include, respectively, bridges that encapsulate transmission/reception data transmitted and received to and from each other and transmit and receive the data to and from each other via the network. Each of the bridges includes a control data transmitting means for generating control data for controlling the state of the system based on control auxiliary data issued from the computer or the device and used for controlling the state of the system, and transmitting the control data to the system management device via the network. The system management device includes a system controlling means for controlling the state of the system in accordance with the control data received thereby.Type: ApplicationFiled: January 19, 2012Publication date: February 27, 2014Applicant: NEC CORPORATIONInventors: Jun Suzuki, Youichi Hidaka, Junichi Higuchi, Takashi Yoshikawa, Teruyuki Baba, Nobuharu Kami
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Patent number: 8635496Abstract: A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements.Type: GrantFiled: August 4, 2009Date of Patent: January 21, 2014Assignee: NEC CorporationInventors: Youichi Hidaka, Takashi Yoshikawa, Junichi Higuchi
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Publication number: 20140016648Abstract: In a switch node connected with an external control server, a high functional service protocol processing can be realized by utilizing a multi-route compatible switch and a network interface (NW I/F), which are prescribed by the PCI express. Specifically, in a system which is provided with a switch node and a control server, a plurality of CPUs having a great deal of memories and a plurality of extended NW I/Fs are connected by a multi-route compatible PCI express switch, to configure a switch port of the plurality of extended NW I/Fs. Load distribution transfer processing to the plurality of CPUs from the network interfaces is made possible. High-speed packet processing is realized through the multiple processing by using the plurality of CPUs. A high-speed switch node is provided in which a large-capacity flow table is configured with the software-based switch node by using a large-capacity memory space of the CPU.Type: ApplicationFiled: March 21, 2012Publication date: January 16, 2014Inventor: Youichi Hidaka
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Patent number: 8625615Abstract: Provided are a first PCI-PCI bridge that handles Multi Root to connect to a plurality of root complexes; a second PCI-PCI bridge that connects to an endpoint; a virtual PCI Express switch that performs a switching process between the first and second PCI-PCI bridges; and a network control device that transfers data that is to be processed in the virtual PCI Express switch to an external switch through a network without passing through a PCI-PCI bridge.Type: GrantFiled: May 18, 2009Date of Patent: January 7, 2014Assignee: NEC CorporationInventors: Youichi Hidaka, Takashi Yoshikawa, Junichi Higuchi, Jun Suzuki
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Publication number: 20130346643Abstract: A CPU 80 controls data transfer from a first device to a second device in a kernel mode. A main memory 90 stores data to be transferred from the first device to the second device. The CPU 80 has: a first device control means 81 which controls the first device; a second device control means which controls the second device; and a data transfer control means 83 which makes a read instruction which instructs the first device control means 81 to store data read from the first device in the main memory 3, and makes a write instruction which instructs the second device control means 82 to write the data stored in the main memory 3 in the second device.Type: ApplicationFiled: February 23, 2012Publication date: December 26, 2013Applicant: NEC CORPORATIONInventors: Jun Suzuki, Masahiko Takahashi, Youichi Hidaka, Teruyuki Baba, Takashi Yoshikawa
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Patent number: 8615623Abstract: A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.Type: GrantFiled: August 8, 2007Date of Patent: December 24, 2013Assignee: NEC CorporationInventors: Youichi Hidaka, Jun Suzuki, Junichi Higuchi, Takashi Yoshikawa
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Patent number: 8565124Abstract: Provided in the EoE technique are the node, the network, the correspondence relationship generating method and the frame transfer program to avoid traffic concentration on a specific link to improve throughput of the network as a whole by realizing optimum path transfer. The frame switching unit includes the frame analysis unit for analyzing an input frame kind and the like, the table search unit for obtaining frame rewriting information and output port information, the forwarding table storage unit for managing an output port of a frame, the MAC learning unit for executing MAC address learning, the EoE-MAC learning unit for learning a relationship between a MAC address and an EoE-MAC address, the STP control unit for executing processing of a spanning tree, and the like.Type: GrantFiled: March 1, 2006Date of Patent: October 22, 2013Assignee: NEC CorporationInventors: Masaki Umayabashi, Kazuo Takagi, Daisaku Ogasahara, Nobuyuki Enomoto, Youichi Hidaka, Atsushi Iwata
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Patent number: 8417865Abstract: An I/O equipment sharing system includes CPUs, a plurality of route complexes coupled to the CPUs, upstream PCI Express-bridges coupled to the route complexes, downstream PCI Express-bridges coupled to the upstream PCI Express-bridges through a network, and I/O equipment coupled to the downstream PCI Express-bridges. In the above configuration, the I/O equipment are shared between the CPUs using the identifiers of the network (for example, Ethernet VLAN IDs), the identifiers are set so that they do not overlap between the respective CPUs and necessary I/O equipment is set to a set identifier. Further, an identifier is set to a plurality of the same I/O equipment required by the respective CPUs.Type: GrantFiled: May 11, 2012Date of Patent: April 9, 2013Assignee: NEC CorporationInventors: Junichi Higuchi, Youichi Hidaka, Jun Suzuki, Atsushi Iwata
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Publication number: 20130086295Abstract: In a switching node, high-speed and advanced service protocol processing function is achieved by utilizing an external control server without affecting performance of conventional service protocol processing. Specifically, a forwarding engine has PCI express and an LAN interface. Depending on a type of an input packet, destination of the packet is switched to the PCI express side for conventional network service and to the LAN interface side for extended network service that cooperates with the external control server. A CPU having the PCI express and the LAN interface is provided ahead of the LAN interface. The CPU performs communication of service inquiry with the external control server at high speed via the LAN interface. After response from the control server is obtained, setting of the forwarding engine is performed through the PCI express.Type: ApplicationFiled: February 18, 2011Publication date: April 4, 2013Inventors: Youichi Hidaka, Masashi Hayashi, Shihomi Sato, Tsugio Okamoto, Takashi Yokota, Masanori Takashima, Koichi Tsuchiya, Minaxay Phila Vongh, Tetsu Izawa