Patents by Inventor Youichi Hidaka

Youichi Hidaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110185163
    Abstract: Provided is an MRA (multi-root aware) PCI express switch accommodating a plurality of root complexes. The MRA PCI express switch includes: a setting register storing necessary information to set a PCI tree based on a switch connection topology and a physical connection state; and a virtual switch bridge controller storing necessary information to establish a virtual PCI tree, irrespective of a status of the setting register. The root complexes can be booted based on the information in the virtual switch bridge controller.
    Type: Application
    Filed: October 14, 2009
    Publication date: July 28, 2011
    Inventor: Youichi Hidaka
  • Publication number: 20110153906
    Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.
    Type: Application
    Filed: March 1, 2011
    Publication date: June 23, 2011
    Applicant: NEC CORPORATION
    Inventors: Jun SUZUKI, Youichi HIDAKA, Junichi HIGUCHI
  • Publication number: 20110145647
    Abstract: A trouble analysis apparatus is provided which includes: a system topology storing portion; an error detection information receiving portion which collects error detection information; and a trouble source determination portion which, based on both the error detection information collected by the error detection information receiving portion and system topology information stored in the system topology information storing portion, determines a trouble source functional element that is presumed as a functional element which is a source of a system trouble. Links included in the system topology information have information indicating spreading directions of error operations between the functional elements when trouble occurs. When the trouble source detection portion receives the error detection information with regard to multiple error functional elements, the trouble source determination portion sequentially selects one of the multiple error functional elements.
    Type: Application
    Filed: August 4, 2009
    Publication date: June 16, 2011
    Inventors: Youichi Hidaka, Takashi Yoshikawa, Junichi Higuchi
  • Patent number: 7917681
    Abstract: A PCI Express switch which connects a plurality of peripheral devices to an arbitrary one of a plurality of CPUs through an Ethernet is constituted by a plurality of upstream and downstream PCI Express-network bridges, an Ethernet switch, and a system manager. Each of the upstream and downstream PCI Express-network bridges includes a PCI Express adapter which terminates a link of a PCI Express bus, a network adapter which terminates a link to the Ethernet switch, and a control unit which encapsulates a TLP in a frame, the destination of which is a MAC address of a bridge to which the destination is connected to transmit and receive the frame. Because the switch according to the present invention comprising a plurality of upstream PCI Express-network bridges and a plurality of downstream PCI Express-network bridges connected to the plurality of upstream PCI Express network bridges through a network is equivalent to a conventional PCI Express switch, it is needless to change a conventional PCI software.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: March 29, 2011
    Assignee: NEC Corporation
    Inventors: Jun Suzuki, Youichi Hidaka, Junichi Higuchi
  • Publication number: 20110064089
    Abstract: Provided are a first PCI-PCI bridge that handles Multi Root to connect to a plurality of root complexes; a second PCI-PCI bridge that connects to an endpoint; a virtual PCI Express switch that performs a switching process between the first and second PCI-PCI bridges; and a network control device that transfers data that is to be processed in the virtual PCI Express switch to an external switch through a network without passing through a PCI-PCI bridge.
    Type: Application
    Filed: May 18, 2009
    Publication date: March 17, 2011
    Inventors: Youichi Hidaka, Takashi Yoshikawa, Junichi Higuchi, Jun Suzuki
  • Patent number: 7894374
    Abstract: A node that configures a spanning tree over a network to which a plurality of nodes are connected generates a tree after a cost change using another LAN while continuing to operate the tree that existed before the change, and switches the tree that is used for forwarding after the new tree has been stable.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: February 22, 2011
    Assignee: NEC Corporation
    Inventors: Nobuyuki Enomoto, Masaki Umayabashi, Youichi Hidaka, Atsushi Iwata, Makoto Shibutani
  • Patent number: 7877521
    Abstract: A virtual PCI Express device 1600 indicates the presence of a pseudo I/O device in a PCI Express initial configuration cycle to reserve a resource space for a device anticipated to be installed in the future, and when an I/O device 1400 is inserted into an unoccupied slot 1605, a virtual PCI Express device control logic 1602 notifies a downstream PCI-PCI bridge 1504 via a hot-plugging control line 1601, and the downstream PCI-PCI bridge 1504 generates an interrupt to a CPU 1100 to notify it of insertion of the I/O device 1400 in conformance with the procedure for hot plugging defined by the PCI-SIG Standards, and configuration software 1000 invoked configures the inserted I/O device 1400.
    Type: Grant
    Filed: August 9, 2007
    Date of Patent: January 25, 2011
    Assignee: NEC Corporation
    Inventors: Jun Suzuki, Youichi Hidaka, Junichi Higuchi, Atsushi Iwata
  • Patent number: 7873056
    Abstract: A switch device is composed of a switch portion 1-1, input side port mapping blocks 1-4-1 to 1-4-P, output side port mapping blocks 1-5-1 to 1-5-P, and a virtualization controller (central controller) 1-0 so that the switch device can be logically divided into a plurality of switches each having a capacity smaller than a physical switch capacity or the divided switches can be logically integrated. The switch portion has a plurality of first input ports and a plurality of first output ports. Each of the input side port mapping blocks has a plurality of second input ports and inputs the signals input to the plurality of second input ports to the first input ports of the switch portion. Each of the output side port mapping blocks has a plurality of second output ports and outputs the signals output to the first output ports of the switch portion from the plurality of second output ports.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: January 18, 2011
    Assignee: NEC Corporation
    Inventors: Junichi Higuchi, Takashi Yoshikawa, Shigeyuki Yanagimachi, Youichi Hidaka
  • Publication number: 20100321902
    Abstract: A connection structure includes housing (10) having insertion/removal openings (11a, 12a) into which and from which a plurality of CPU cards (6), in which electronic parts are mounted on a circuit board, and switch cards (7) are inserted and removed, back plane (13) to which cards (6, 7) are electrically connected, and optical circuit board (14) that is optically connected to optical connectors (16) which are arranged on cards (6, 7) so as to be exposed to the outside of housing (10) from insertion/removal openings (11a, 12a) with cards (6, 7) connected to back plane (13).
    Type: Application
    Filed: November 26, 2007
    Publication date: December 23, 2010
    Inventors: Ichiro Hatakeyama, Shigeyuki Yanagimachi, Youichi Hidaka, Ichiro Ogura
  • Patent number: 7855981
    Abstract: A node that configures a spanning tree over a network to which a plurality of nodes are connected generates a tree after a cost change using another LAN while continuing to operate the tree that existed before the change, and switches the tree that is used for forwarding after the new tree has been stable.
    Type: Grant
    Filed: March 4, 2008
    Date of Patent: December 21, 2010
    Assignee: NEC Corporation
    Inventors: Nobuyuki Enomoto, Masaki Umayabashi, Youichi Hidaka, Atsushi Iwata, Makoto Shibutani
  • Publication number: 20100257302
    Abstract: Upstream network interfaces (2-1-2-N) and downstream network interfaces (5-1-5-M) have an upstream PCI-PCI bridge function and a downstream PCI-PCI bridge function, respectively. These network interfaces (2-1-2-N, 5-1-5-M) and a network (3) are incorporated in a system as a single multi-root PCI express switch. The network (3) tunnels TLPs (Transaction Layer Packets) between the upstream network interfaces (2-1-2-N) and the downstream network interfaces (5-1-5-M) or between the downstream network interfaces (5-1-5-M). This enables to distribute and connect a plurality of computers and a plurality of I/Os on a large scale without changing software, root complexes, and I/Os.
    Type: Application
    Filed: October 27, 2008
    Publication date: October 7, 2010
    Inventors: Jun Suzuki, Youichi Hidaka, Takashi Yoshikawa
  • Publication number: 20100232322
    Abstract: For eliminating a reduction in throughput in a network as a whole according to optimum path transfer technique which is the expansion of spanning tree protocol, a frame switching unit of the network has an STP control unit for, when a port state of a spanning tree is changed, notifying a table control unit of an identifier of the spanning tree and a port number of a predetermined port among the respective ports, the table control unit for setting, in a forwarding table storage unit, a received port number of a predetermined port as an output port in an entry in which a node ID is equivalent to a spanning tree identifier, and a table search unit for determining an output destination from among output ports obtained by acquisition of received frame information from a frame analysis unit.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 16, 2010
    Applicant: NEC Corporation
    Inventors: Masaki Umayabashi, Nobuyuki Enomoto, Youichi Hidaka, Daisaku Ogasahara, Kazuo Takagi, Atsushi Iwata
  • Patent number: 7783705
    Abstract: A node to relay the Ethernet frame provided with means to insert, in the relay process of the frame, two or more VLAN tags into the frame at a time and to remove the inserted VLAN tags wherein a TTL area to show the frame survival time is provided in the VLAN tag to be inserted to the frame so that whether the survival time has been elapsed or not is checked by the value in the TTL area and the frame after elapse of the survival time is discarded without being relayed.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: August 24, 2010
    Assignee: NEC Corporation
    Inventors: Youichi Hidaka, Makoto Shibutani, Atsushi Iwata, Masaki Umayabashi, Nobuyuki Enomoto
  • Publication number: 20100180062
    Abstract: A switch (304) includes a plurality of bridges (3041, 3042, 3043, 3044, 3045) and a switch forwarding mechanism (20). Each of the bridges transmits and receives a TLP frame complying with PCI express to and from a device connected to each of the bridges. The switch forwarding mechanism includes a plurality of ports (1, 2, 3, 4, 5) to which the bridges are connected, respectively, selects an output port in dependence on a combination of destination information on the TLP frame input from one of the plurality of ports and the port which input the TLP frame, and outputs the TLP frame from the selected output port.
    Type: Application
    Filed: August 8, 2007
    Publication date: July 15, 2010
    Inventors: Youichi Hidaka, Jun Suzuki, Junichi Higuchi, Takashi Yoshikawa
  • Publication number: 20100154049
    Abstract: [Problems to be solved] To provide a system capable of controlling a PC firewall responding to a location, thereby to prevent a third person from intruding into a PC without being restricted by an application. [Means to solve the problems] A first security system includes: a network recognizing unit for performing a test for confirming whether an IP address allotted to the PC coincides with a specification value, and notifying its test result to a security setting unit; the security setting unit for, upon receipt of the test result from the network recognizing unit, notifying a setting modification command to a firewall unit based upon its test result; and the firewall unit for, upon receipt of the setting modification command from the security setting unit, executing a packet filtering responding to its command.
    Type: Application
    Filed: June 27, 2006
    Publication date: June 17, 2010
    Applicant: NEC CORPORATION
    Inventors: Hideo Yoshimi, Nobuyuki Enomoto, Youichi Hidaka, Atsushi Iwata, Kazuo Takagi
  • Publication number: 20090175281
    Abstract: A switch device is composed of a switch portion 1-1, input side port mapping blocks 1-4-1 to 1-4-P, output side port mapping blocks 1-5-1 to 1-5-P, and a virtualization controller (central controller) 1-0 so that the switch device can be logically divided into a plurality of switches each having a capacity smaller than a physical switch capacity or the divided switches can be logically integrated. The switch portion has a plurality of first input ports and a plurality of first output ports. Each of the input side port mapping blocks has a plurality of second input ports and inputs the signals input to the plurality of second input ports to the first input ports of the switch portion. Each of the output side port mapping blocks has a plurality of second output ports and outputs the signals output to the first output ports of the switch portion from the plurality of second output ports.
    Type: Application
    Filed: November 18, 2005
    Publication date: July 9, 2009
    Applicant: NEC CORPORATION
    Inventors: Junichi Higuchi, Takashi Yoshikawa, Shigeyuki Yanagimachi, Youichi Hidaka
  • Patent number: 7532588
    Abstract: A node of a spanning tree system operating on a network connecting a plurality of nodes, comprises two transfer units which determines an output destination port, based on the destination MAC address of an input frame, two tree managers which configures a spanning tree according to a spanning tree protocol, and a virtual port of connecting the tree manager and the transfer unit.
    Type: Grant
    Filed: August 18, 2003
    Date of Patent: May 12, 2009
    Assignee: NEC Corporation
    Inventors: Nobuyuki Enomoto, Masaki Umayabashi, Youichi Hidaka, Atsushi Iwata
  • Publication number: 20090059928
    Abstract: Any packet loss is detected very quickly by means of only a series of sequence number in a multi-path environment where a transmitter and a receiver are connected to each other by way of a plurality of networks when no inversion of sequence arises in any of the networks. A communication apparatus includes a plurality of sequence buffers arranged at each network to accumulate packets until a sequence acknowledgement and an absence detecting section adapted to determine the occurrence of an absence of a packet when one or more packets are accumulated in all the sequence buffers. With this arrangement, the absence detecting section of the receiver monitors the packets staying in the sequence guaranteeing buffer arranged in each of the network, paying attention to the characteristic that packets are stored in the sequence buffers of all the networks when a packet loss takes place.
    Type: Application
    Filed: August 28, 2008
    Publication date: March 5, 2009
    Applicant: NEC CORPORATION
    Inventors: Nobuyuki Enomoto, Hideyuki Shimonishi, Junichi Higuchi, Youichi Hidaka, Jun Suzuki, Takashi Yoshikawa
  • Publication number: 20090037587
    Abstract: Out of data being transmitted from a client application A1 to a server application B1, data of which encryption has been determined to be necessary in a frame analyzing means within an intermediate driver A11 of s PC 1 is relayed by use of a total of two TCP sessions consisting of a TCP session 1 between a TCP A14 and a TCP A2, and a TCP session 2 between a TCP A17 and a TCP B3. Relaying the TCP sessions in such a manner makes it possible to achieve a coincidence of a TCP/IP protocol hierarchy between an SSL A16 within the intermediate driver A11 and an SSL B2 within a server 2, which enables certificate information, an encryption algorithm, etc. necessary for starting an SSL session to be automatically exchanged therebetween. As a result, secret data being sent out from the PC can be encrypted without changing the setting of the server or installing any software.
    Type: Application
    Filed: February 27, 2006
    Publication date: February 5, 2009
    Applicant: NEC CORPORATION
    Inventors: Hideo Yoshimi, Nobuyuki Enomoto, Youichi Hidaka
  • Publication number: 20090028140
    Abstract: A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.
    Type: Application
    Filed: June 2, 2006
    Publication date: January 29, 2009
    Applicant: NEC Corporation
    Inventors: Junichi Higuchi, Youichi Hidaka, Mikiharu Yamashita, Yukihiro Hara