Abstract: An electronic device according to various embodiments of the present invention may comprise: a housing comprising a first surface facing in a first direction and a second surface facing in a second direction that is opposite to the first direction, the first surface comprising an at least partially transparent part and at least one opening formed adjacent to the at least partially transparent part; a camera positioned inside the housing, the camera comprising an image sensor facing in the first direction through the at least partially transparent part of the housing; and an acoustic component arranged between the first surface and the second surface, the acoustic component comprising a vibration plate configured to generate a sound such that the same moves in at least one direction selected from the first and second directions, a first passage formed in a third direction that is substantially perpendicular to the first direction such that the generated sound passes through the same, and a second passage forme

Abstract: A scrubber system may include a scrubber housing including a vertically extended cleaning space, an inflow chamber coupled to a bottom portion of the scrubber housing, and first and second inflow portions, each of which is configured to supply a gas into the inflow chamber. The inflow chamber may include a mixing space, and the mixing space may be connected to the cleaning space. The first inflow portion may include a first connection pipe coupled to the inflow chamber to provide a first connection path and the second inflow portion may include a second connection pipe coupled to the inflow chamber to provide a second connection path. The first and second connection paths may be extended toward the mixing space in opposite directions, respectively, and may be connected to opposite portions of the mixing space, respectively.

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including electrodes vertically stacked on the substrate and each having a pad portion, electrode separation structures penetrating the electrode structure and apart from each other in a second direction, and contact plugs coupled to the pad portions. The contact plugs comprise first contact plugs and second contact plugs apart in the second direction from the first contact plugs. The electrode separation structures comprise a first electrode separation between the first and second contact plugs. The first contact plugs are apart in the second direction at a first distance from the first electrode separation structure. The second contact plugs are apart in the second direction from the first electrode separation structure at a second distance, different from the first distance.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: A three-dimensional semiconductor memory device includes a substrate, an electrode structure including electrodes vertically stacked on the substrate and each having a pad portion, electrode separation structures penetrating the electrode structure and apart from each other in a second direction, and contact plugs coupled to the pad portions. The contact plugs comprise first contact plugs and second contact plugs apart in the second direction from the first contact plugs. The electrode separation structures comprise a first electrode separation between the first and second contact plugs. The first contact plugs are apart in the second direction at a first distance from the first electrode separation structure. The second contact plugs are apart in the second direction from the first electrode separation structure at a second distance, different from the first distance.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate linesare spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.

Abstract: Three-dimensional (3D) semiconductor memory devices and methods of manufacturing the same are provided. Three-dimensional (3D) semiconductor memory devices may include a substrate including a cell array region and a connection region, a lower stack structure including a plurality of lower electrodes vertically stacked on the substrate, the lower stack structure having a first stair step structure extending in a first direction on the connection region and a second stair step structure extending in a second direction substantially perpendicular to the first direction on the connection region, and a plurality of intermediate stack structures vertically stacked on the lower stack structure. Each of the intermediate stack structures includes a plurality of intermediate electrodes vertically stacked and has a third stair step structure extending in the second direction on the connection region.

Abstract: In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.

Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.

Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.

Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.

Abstract: A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.

Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.