Patents by Inventor Young-bae Yoon
Young-bae Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120276729Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.Type: ApplicationFiled: July 10, 2012Publication date: November 1, 2012Inventors: Young-bae YOON, Jeong-dong Choe, Hee-soo Kang, Dong-hoon Jang, Ki-hyun Kim
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Patent number: 8208301Abstract: Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings.Type: GrantFiled: October 5, 2009Date of Patent: June 26, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Hee-soo Kang, Choong-ho Lee, Yoon-moon Park, Dong-hoon Jang, Young-bae Yoon
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Publication number: 20120045901Abstract: In a method of forming a pattern structure, a cut-off portion of the node-separated line of a semiconductor device is formed by a double patterning process by using a connection portion of the sacrificial mask pattern and the mask pattern to thereby improve alignment margin. The alignment margin between the mask pattern and the sacrificial mask pattern is increased to an amount of the length of the connection portion of the sacrificial mask pattern. The lines adjacent to the node-separated line include a protrusion portion protruding toward the cut-off portion of the separated line.Type: ApplicationFiled: August 18, 2011Publication date: February 23, 2012Inventors: JONG-HYUK KIM, Keon-Soo Kim, Kwang-Shik Shin, Hyun-Chul Back, Seong-Soon Cho, Young-Bae Yoon, Jung-Hwan Park
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Publication number: 20120015496Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.Type: ApplicationFiled: September 22, 2011Publication date: January 19, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-Bae YOON, Jeong-Dong Choe, Dong-Hoon Jang, Ki-Hyun Kim
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Publication number: 20120009759Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: ApplicationFiled: September 20, 2011Publication date: January 12, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Dong-hoon JANG, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Patent number: 8059469Abstract: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.Type: GrantFiled: June 10, 2009Date of Patent: November 15, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Se-Hoon Lee, Choong-Ho Lee, Jeong-Dong Choe, Tae-Yong Kim, Woo-Jung Kim, Dong-Hoon Jang, Young-Bae Yoon, Ki-Hyun Kim, Min-Tai Yu
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Patent number: 8039905Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.Type: GrantFiled: March 11, 2009Date of Patent: October 18, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Bae Yoon, Jeong-Dong Choe, Dong-Hoon Jang, Ki-Hyun Kim
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Patent number: 8035152Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: GrantFiled: June 22, 2009Date of Patent: October 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Publication number: 20110038211Abstract: A semiconductor memory device and method of manufacturing the same, the device including string structures, the string structures including two or more adjacent string selection transistors connected in series to each other in a first direction and being spaced apart from one another in a second direction intersecting the first direction, the two or more string selection transistors having different threshold voltages; string selection lines, the string selection lines connecting the adjacent string selection transistors of the string structures in the second direction; and a bit line electrically connecting two or more adjacent string structures, wherein a device isolation layer between the adjacent string selection transistors in the second direction has recessed regions, and profiles of the recessed regions on respective sides of the string selection transistors are different from each other.Type: ApplicationFiled: July 8, 2010Publication date: February 17, 2011Inventors: Young-Bae Yoon, Jong-Hyuk Kim, Keonsoo Kim, Youngseop Rah, Yoonmoon Park
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Publication number: 20100085812Abstract: Provided is a nonvolatile memory device having a common bit line structure. The nonvolatile memory device includes multiple unit elements having a NAND cell array structure, arranged in each of multiple memory strings, and each including a control gate and a charge storage layer. Multiple common bit lines are each commonly connected to ends of each of one pair of memory strings among the memory strings. Provided are a first selection transistor having a first driving voltage and multiple second selection transistors connected in series to the first selection transistors and having a second driving voltage that is lower than the first driving voltage. The first selection transistor and the second selection transistors are arranged between the common bit lines and the unit elements of the of memory strings. A first string selection line is connected to one of the first and second selection transistors of a first memory string of one pair of memory strings that are connected to one of the common bit lines.Type: ApplicationFiled: October 5, 2009Publication date: April 8, 2010Inventors: Hee-soo Kang, Choong-ho Lee, Yoon-moon Park, Dong-hoon Jang, Young-bae Yoon
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Publication number: 20100008152Abstract: A semiconductor device includes a driving active region defined in a substrate and at least three driving transistors disposed at the driving active region. The driving transistors share one common source/drain, and each of the driving transistors includes individual source/drains being independent from each other. The common source/drain and the individual source/drains are disposed in the driving active region.Type: ApplicationFiled: June 10, 2009Publication date: January 14, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Se-Hoon Lee, Choong-Ho Lee, Jeong-Dong Choe, Tae-Yong Kim, Woo-Jung Kim, Dong-Hoon Jang, Young-Bae Yoon, Ki-Hyun Kim, Min-Tai Yu
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Publication number: 20100001366Abstract: A semiconductor device, including a substrate having first and second active regions, the first and second active regions being disposed on opposite sides of an isolation structure, and a bit line electrically coupled to a contact plug that is on the isolation structure between the first active region and the second active region, and electrically coupled to an active bridge pattern directly contacting at least one of the first and second active regions, wherein the contact plug is electrically coupled to the first active region and the second active region, and a bottom surface of the active bridge pattern is below a top surface of the first and second active regions.Type: ApplicationFiled: June 22, 2009Publication date: January 7, 2010Inventors: Dong-hoon Jang, Young-bae Yoon, Hee-soo Kang, Young-seop Rah, Jeong-dong Choe
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Publication number: 20090302472Abstract: Provided are non-volatile memory devices and methods of fabricating the same, including improved bit line and contact formation that may reduce resistance and parasitic capacitance, thereby reducing manufacturing costs and improving device performance. The non-volatile memory devices may include a substrate; a plurality of field regions formed on the substrate, each of the field regions including a homogeneous first field and a second field that is divided into two sub regions via a bridge region; an active region formed on the substrate and defined as having a string structure by the field regions, where at least two strings may be connected via one of the bridge regions; and a plurality of shared bit lines may be formed on the field regions and connected to the active region via bit line contacts, where the bit line contacts may be direct contacts.Type: ApplicationFiled: May 28, 2009Publication date: December 10, 2009Inventors: Young-bae Yoon, Jeong-dong Choe, Hee-soo Kang, Dong-hoon Jang, Ki-hyun Kim
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Publication number: 20090230456Abstract: A semiconductor device includes a substrate having a first area and a second area, a first transistor in the first area, a second transistor in the second area, an isolation layer between the first area and the second area, and at least one buried shield structure on the isolation layer.Type: ApplicationFiled: March 11, 2009Publication date: September 17, 2009Inventors: Young-Bae Yoon, Jeong-Dong Choe, Dong-Hoon Jang, Ki-Hyun Kim
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Publication number: 20090001346Abstract: The present invention relates to non-volatile memory device utilizing multi-layered self-assembled Ni1-xFex nanocrystalline arrays embedded in a polymer thin film without source and drain regions and the fabrication method thereof. It is possible to fabricate nano-crystallines more simply than hitherto method according to the present invention. More particularly, it is possible to control size and density of nano-crystallines without agglomeration of the crystallines since the crystallines, which have uniform distribution, are besieged to polymer layer. Furthermore, the present invention provides the non-volatile bistable memory device having chemical and electrical stability of higher efficiency and lower cost than conventional flash memory devices with a nano floating gate. Also, source and drain region is unnecessary in the device of the present invention, it can reduce the throughput time and cost.Type: ApplicationFiled: September 26, 2005Publication date: January 1, 2009Applicants: SAMSUNG ELECTRONICS CO., LTD., INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITYInventors: Tae-whan Kim, Young-ho Kim, Jae-ho Kim, Jae-hum Jung, Young-bae Yoon, Sung-keun Lim
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Publication number: 20070269916Abstract: An organic light emitting diode (OLED) display includes a substrate, a first electrode disposed on the substrate, a second electrode facing the first electrode, an emission layer disposed between the first electrode and the second electrode, and a hole transport layer disposed between the first electrode and the emission layer. The hole transport layer includes a first hole transport layer comprised of a first material, a second hole transport layer comprised of a combination of the first material and a second material, and a third hole transport layer comprised of the first material. The second material has a different band gap energy from that of the first material, and the second hole transport layer and the third hole transport layer are alternately and repeatedly disposed.Type: ApplicationFiled: March 20, 2007Publication date: November 22, 2007Inventors: Tae-Whan KIM, Young-Bae Yoon
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Publication number: 20070048548Abstract: A hole blocking layer, having a multiple hetero-structure such that materials, each with a different doping density, are stacked repeatedly, is formed between a hole transport layer and an electron transport layer. An organic light emitting device and its manufacturing method can enhance luminous efficiency and color stability having the abovementioned hole blocking layer.Type: ApplicationFiled: August 22, 2006Publication date: March 1, 2007Inventors: Tae-Whan Kim, Young-Bae Yoon
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Publication number: 20070024188Abstract: An organic light emitting device, and a manufacturing method thereof, in which the organic light emitting device includes a mixture layer forming a stepwise concentration gradient by mixing a hole transport layer material and an electron transport layer material formed at an interface between an electron transport layer and an emission layer and also at an interface between a hole transport layer and the emission layer. The emission layer has a structure in which a unit layer and a quantum well layer are repeatedly laminated wherein the unit layer is formed by mixing the hole transport layer material, the electron transport layer material, and the material for transferring energy to the light emitting material, and then coated with the light emitting material.Type: ApplicationFiled: July 28, 2006Publication date: February 1, 2007Inventors: Tae-Whan Kim, Young-bae Yoon