Patents by Inventor Young-Jin Noh
Young-Jin Noh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240121955Abstract: A manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.Type: ApplicationFiled: March 21, 2023Publication date: April 11, 2024Applicant: SK hynix Inc.Inventors: Jong Gi KIM, Young Jin NOH, Jae O PARK, Jin Ho BIN, Dong Chul YOO, Yoo Il JEON
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Publication number: 20230047219Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.Type: ApplicationFiled: October 27, 2022Publication date: February 16, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Soo Lee, Yoshihisa Hirano, Jae Hoon KIm, Young Jin Noh, Sung Moon Park, Seung Kyu Lim, Kyeong Seok Jeong, Hyung Kyu Choi
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Publication number: 20230044703Abstract: Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.Type: ApplicationFiled: October 25, 2022Publication date: February 9, 2023Inventors: SEUNG BO SHIM, DOUG YONG SUNG, YOUNG JIN NOH, YONG WOO LEE, JI SOO IM, HYEONG MO KANG, PETER BYUNG H HAN, CHEON KYU LEE, MASATO HORIGUCHI
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Patent number: 11501953Abstract: Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.Type: GrantFiled: March 22, 2019Date of Patent: November 15, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Seung Bo Shim, Doug Yong Sung, Young Jin Noh, Yong Woo Lee, Ji Soo Im, Hyeong Mo Kang, Peter Byung H Han, Cheon Kyu Lee, Masato Horiguchi
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Publication number: 20220172926Abstract: A method for fabricating a semiconductor device includes providing a wafer on a lower electrode inside a plasma processing apparatus. A first power having a first and second frequency is provided to the lower electrode. A second power is provided to an RF induction electrode through the lower electrode. A third power having the second frequency is released outside of a chamber. A plasma process is performed on the wafer while the third power is released. The RF induction electrode is disposed inside an insulating plate surrounding a sidewall of the lower electrode. The RF induction electrode is spaced apart front the lower electrode. The RF induction electrode has an annular shape surrounding the sidewall of the lower electrode. The first power is controlled by a first controller, and the third power is controlled by a second controller different from the first controller.Type: ApplicationFiled: July 27, 2021Publication date: June 2, 2022Inventors: Dong Wan Kim, Beom Rae Kim, Dong Hyeon Na, Young Jin Noh, Seung Bo Shim, Sang-Ho Lee, Yong Woo Lee, Jun Ho Lee, Dong Hee Han
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Publication number: 20220102513Abstract: A semiconductor memory device includes: a tunnel insulating layer disposed between a conductive pattern and a channel layer; a data storage layer disposed between the conductive pattern and the tunnel insulating layer, the data storage layer including a silicon nitride layer; a first blocking insulating layer disposed between the conductive pattern and the data storage layer; a second blocking insulating layer disposed between the conductive pattern and the first blocking insulating layer; and a carbon containing layer disposed at at least one position among a position between the tunnel insulating layer and the data storage layer, a position between the first blocking insulating layer and the data storage layer, a position in the tunnel insulating layer, and a position between the first blocking insulating layer and the second blocking insulating layer.Type: ApplicationFiled: March 29, 2021Publication date: March 31, 2022Applicant: SK hynix Inc.Inventors: Jin Ho BIN, Il Young KWON, Tae Hong GWON, Seok Joo KIM, Su Jin NOH, Young Jin NOH, Jae O PARK, Jin Ho OH, Dong Chul YOO, Jae Jin YUN, Su Hyun LEE, Yoo Il JEON
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Publication number: 20200258753Abstract: A plasma processing apparatus may include a lower electrode supporting a wafer; a focus ring surrounding an edge of the lower electrode and having a ring shape; and an edge ring disposed in a position lower than a position of the focus ring. The focus ring may include a lower region and an upper region disposed on the lower region, and the upper region increases in electrical conductivity as the upper region is closer to the lower region.Type: ApplicationFiled: October 9, 2019Publication date: August 13, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jun Soo LEE, Yoshihisa Hirano, Jae Hoon Kim, Young Jin Noh, Sung Moon Park, Seung Kyu Lim, Kyeong Seok Jeong, Hyung Kyu Choi
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Patent number: 10720447Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: July 16, 2019Date of Patent: July 21, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Publication number: 20190341400Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: July 16, 2019Publication date: November 7, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10440821Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.Type: GrantFiled: April 4, 2018Date of Patent: October 8, 2019Assignee: LG INNOTEK CO., LTD.Inventors: Dong Youl Lee, Young Jin Noh, Young Sun You, Sun Young Lee, Yong Jin Lee, Kyoung Hoon Chai
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Publication number: 20190304754Abstract: Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.Type: ApplicationFiled: March 22, 2019Publication date: October 3, 2019Inventors: SEUNG BO SHIM, DOUG YONG SUNG, YOUNG JIN NOH, YONG WOO LEE, JI SOO IM, HYEONG MO KANG, PETER BYUNG H HAN, CHEON KYU LEE, MASATO HORIGUCHI
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Patent number: 10411034Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: GrantFiled: June 7, 2018Date of Patent: September 10, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10355099Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.Type: GrantFiled: January 14, 2018Date of Patent: July 16, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Eun Yeoung Choi, Jun Kyu Yang, Young Jin Noh, Jae Young Ahn, Jae Hyun Yang, Dong Chul Yoo, Jae Ho Choi
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Publication number: 20190157293Abstract: An integrated circuit memory device includes a vertical stack structure containing an interlayer insulating layer and a gate electrode, on a substrate. A blocking dielectric region is provided on a sidewall of an opening in the stack structure. A lateral impurity region is provided, which extends between the blocking dielectric region and the interlayer insulating layer and between the blocking dielectric region and the gate electrode. A lower impurity region is also provided, which extends between the blocking dielectric region and the substrate.Type: ApplicationFiled: June 7, 2018Publication date: May 23, 2019Inventors: Woo Jin Jang, Young Jin Noh, Jun Kyu Yang, Bio Kim, Kyong Won An
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Patent number: 10283382Abstract: A plasma processing apparatus including an electrostatic chuck supporting a wafer; a focus ring disposed to surround an outer circumferential surface of the wafer; an insulation ring disposed to surround an outer circumferential surface of the focus ring; and an edge ring supporting lower portions of the focus ring and the insulation ring, the edge ring being spaced apart from the electrostatic chuck and surrounding an outer circumferential surface of the electrostatic chuck; wherein the edge ring includes a flow channel containing a fluid therein.Type: GrantFiled: August 9, 2017Date of Patent: May 7, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Noh, Kyung Sun Kim, Seung Bo Shim, Yong Woo Lee, Ji Soo Im, Won Young Choi
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Patent number: 10224185Abstract: A substrate processing apparatus including a process chamber configured to receive a plurality of substrates oriented in a horizontal manner and vertically arranged with respect to the process chamber, a process gas supply unit configured to supply at least one process gas to the process chamber through a process gas supply nozzle, the process gas supply nozzle along an inner wall of the process chamber in a direction in which the substrates are sacked, an exhaust unit configured to exhaust the process gas from the process chamber, and a blocking gas supply unit configured to supply a blocking gas through a blocking gas injector provided in a circumferential direction of the process chamber such that a flow of the process gas in the process chamber is controlled may be provided.Type: GrantFiled: April 17, 2015Date of Patent: March 5, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Young-jin Noh, Kwang-min Park, Eun-sung Seo, Young-chang Song, Jae-young Ahn, Hun-hyeong Lim, Ji-hoon Choi
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Publication number: 20180366554Abstract: A plurality of gate electrodes is stacked on an upper surface of a substrate in a direction perpendicular to an upper surface of the substrate. A channel region penetrates through the plurality of gate electrodes to extend perpendicularly to the upper surface of the substrate. A gate dielectric layer includes a tunneling layer, a charge storage layer and a blocking layer that are sequentially disposed between the channel region and the plurality of gate electrodes. The charge storage layer includes a plurality of doping elements and a plurality of deep level traps generated by the plurality of doping element. A concentration distribution of the plurality of doping elements in a thickness direction of the charge storage layer is non-uniform.Type: ApplicationFiled: January 14, 2018Publication date: December 20, 2018Inventors: Eun Yeoung CHOI, Jun Kyu YANG, Young Jin NOH, Jae Young AHN, Jae Hyun YANG, Dong Chul YOO, Jae Ho CHOI
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Publication number: 20180228025Abstract: Provided is a touch panel. The touch panel includes a substrate and an electrode member disposed on the substrate. The electrode member includes a base material for electrode having first and second surfaces opposite to each other, a first electrode disposed on the first surface, and a second electrode disposed on the second surface.Type: ApplicationFiled: April 4, 2018Publication date: August 9, 2018Inventors: DONG YOUL LEE, YOUNG JIN NOH, YOUNG SUN YOU, SUN YOUNG LEE, YONG JIN LEE, KYOUNG HOON CHAI
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Patent number: 10041170Abstract: Provided are a dummy wafer, a thin-film forming method, and a method of fabricating a semiconductor device using the same. The dummy wafer includes an insulating substrate with a first surface opposite a second surface, and a plurality of openings formed in the insulating substrate. The plurality of openings penetrate at least a portion of the insulating substrate in a direction from the first surface toward the second surface. The first and second surfaces of the insulating substrate, and an inner surface of each of the plurality of openings, include protrusions.Type: GrantFiled: August 4, 2016Date of Patent: August 7, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Cheolkyu Yang, Young-Jin Noh, Chulyoung Jang, Joongyun Ra, Dong-min Son
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Patent number: 10020234Abstract: A method for fabricating a substrate includes forming a first substrate including a thin film transistor array, and inspecting a first surface of an inspecting device, wherein inspecting the first surface of the inspection device includes: generating first measurement data by detecting a first measurement light that is parallel to a surface of an inspection region in the first surface, generating second measurement data by detecting a second measurement light that is parallel to the surface of the inspection region, and inspecting a state of a surface of the inspection region by comparing the first measurement data with the second measurement data.Type: GrantFiled: August 10, 2016Date of Patent: July 10, 2018Assignees: SAMSUNG ELECTRONICS CO., LTD., SAMSUNG DISPLAY CO., LTD.Inventors: Young-Jin Noh, Jung-Sub Lee, Sung-Mo Gu