Patents by Inventor Young-Jun Yoon
Young-Jun Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11049530Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.Type: GrantFiled: October 27, 2020Date of Patent: June 29, 2021Assignee: SK hynix Inc.Inventors: Young Jun Yoon, Hyun Seung Kim
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Patent number: 10936409Abstract: A memory system comprises: a memory cell array suitable for storing first data and a first parity, which is used to correct an error of the first data; and an error correcting circuit suitable for generating second data and a second parity, which includes bits obtained by correcting an error of the first parity and a bit obtained by correcting an error of a second sub-parity; wherein the error correcting circuit includes: a single error correction and double error detection (SECDED) parity generator suitable for generating a second pre-parity, which includes a first sub-parity and the second sub-parity; a syndrome decoder suitable for generating a first parity error flag and a first data error flag by decoding a syndrome; a SEC parity corrector suitable for correcting an error of the first parity based on the first parity error flag; a DED parity error detector suitable for generating a second sub-parity error flag based on an error information of the first data used to generate the second sub-parity; and a DType: GrantFiled: November 26, 2018Date of Patent: March 2, 2021Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Ki-Up Kim, Young-Jun Yoon
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Publication number: 20210043237Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.Type: ApplicationFiled: October 27, 2020Publication date: February 11, 2021Applicant: SK hynix Inc.Inventors: Young Jun YOON, Hyun Seung KIM
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Publication number: 20210043236Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.Type: ApplicationFiled: October 27, 2020Publication date: February 11, 2021Applicant: SK hynix Inc.Inventors: Young Jun YOON, Hyun Seung KIM
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Patent number: 10901926Abstract: A semiconductor device includes a burst control circuit configured to generate burst information depending on a logic level of a setting bit when an operation setting signal is inputted and configured to generate a burst control signal from the burst information in the case where a read signal is inputted. The semiconductor device also includes a data processing circuit configured to output output data by performing first and second burst operations for internal data, depending on a logic level of the burst control signal.Type: GrantFiled: May 1, 2019Date of Patent: January 26, 2021Assignee: SK hynix Inc.Inventors: Woongrae Kim, Young Jun Yoon
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Patent number: 10861515Abstract: An operating method for a semiconductor memory device includes: generating a whole-domain-crossing-unit reset signal based on a domain-crossing-unit reset signal input to a whole-domain-crossing-unit-reset-signal generator; and resetting a counter synchronized to a data clock of a domain-crossing unit based on the whole-domain-crossing-unit reset signal during a data clock preparation section in which the data clock does not toggle.Type: GrantFiled: September 12, 2018Date of Patent: December 8, 2020Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Sang-Sic Yoon, Young-Jun Yoon
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Patent number: 10854248Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.Type: GrantFiled: November 2, 2018Date of Patent: December 1, 2020Assignee: SK hynix Inc.Inventors: Young Jun Yoon, Hyun Seung Kim
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Patent number: 10784706Abstract: A wireless power transmitter configured to wirelessly transmit power to an electronic device is provided.Type: GrantFiled: May 11, 2018Date of Patent: September 22, 2020Assignees: Samsung Electronics Co., Ltd., SEOUL NATIONAL UNIVERSITY R&DB FOUNDATIONInventors: Chong-Min Lee, Seong-Cheol Kim, Dae-Hyun Kim, Sang-Wook Lee, Young-Ho Ryu, Byeong-Ho Lee, Seong-Wook Lee, Young-Jun Yoon
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Patent number: 10755761Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.Type: GrantFiled: October 15, 2019Date of Patent: August 25, 2020Assignee: SK hynix Inc.Inventors: Sang Kwon Lee, Kwang Soon Kim, Young Hoon Kim, Young Jun Yoon, Kyu Dong Hwang
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Patent number: 10726885Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.Type: GrantFiled: August 7, 2019Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventors: Yoo Jong Lee, Kang Sub Kwak, Young Jun Yoon
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Patent number: 10720192Abstract: A semiconductor device includes a strobe signal generation circuit. The strobe signal generation circuit generates a strobe signal which is toggled in synchronization with a multiplication clock signal during enablement periods of a toggling drive signal and a down drive signal. A postamble period is set according to the toggling drive signal and the down drive signal.Type: GrantFiled: November 26, 2018Date of Patent: July 21, 2020Assignee: SK hynix Inc.Inventor: Young Jun Yoon
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Publication number: 20200219546Abstract: A semiconductor system includes a controller and a semiconductor device. The controller outputs a clock signal, a chip selection signal and a command/address signal. The controller includes a controller termination circuit turned on during a read operation. The controller receives first data through an input/output (I/O) line coupled to the controller termination circuit during the read operation and outputs second data through the I/O line coupled to the controller termination circuit turned off during a write operation. The semiconductor device includes an internal termination circuit turned off during the read operation, outputs the first data through the I/O line coupled to the internal termination circuit based on the chip selection signal and the command/address signal during the read operation, and stores the second data inputted through the I/O line coupled to the internal termination circuit turned on during the write operation.Type: ApplicationFiled: August 7, 2019Publication date: July 9, 2020Applicant: SK hynix Inc.Inventors: Yoo Jong LEE, Kang Sub KWAK, Young Jun YOON
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Publication number: 20200192747Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
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Publication number: 20200192746Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Applicant: SK hynix Inc.Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
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Publication number: 20200192748Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: ApplicationFiled: February 26, 2020Publication date: June 18, 2020Inventors: Kang-Sub KWAK, Young-Jun YOON, Joon-Yong CHOI
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Patent number: 10656790Abstract: A display apparatus and a method for displaying a screen in a display apparatus are provided. The display apparatus and method of displaying a screen in a display apparatus includes setting an area of a display screen as a user designated area through an area designation user interface (UI) and when a preset event is generated, displaying at least one of a graphical user interface (GUI) and a portion of the display screen in the set user designated area, depending on the generated event type.Type: GrantFiled: September 21, 2015Date of Patent: May 19, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Min-kyoung Yoon, Sang-ok Cha, Young-jun Yoon, Joo-yeon Cho
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Publication number: 20200142847Abstract: A semiconductor device includes a burst control circuit configured to generate burst information depending on a logic level of a setting bit when an operation setting signal is inputted and configured to generate a burst control signal from the burst information in the case where a read signal is inputted. The semiconductor device also includes a data processing circuit configured to output output data by performing first and second burst operations for internal data depending on a logic level of the burst control signal.Type: ApplicationFiled: May 1, 2019Publication date: May 7, 2020Applicant: SK hynix Inc.Inventors: Woongrae KIM, Young Jun YOON
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Patent number: 10606689Abstract: A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.Type: GrantFiled: April 12, 2018Date of Patent: March 31, 2020Assignee: SK hynix Inc.Inventors: Kang-Sub Kwak, Young-Jun Yoon, Joon-Yong Choi
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Patent number: 10559332Abstract: A semiconductor device includes a synthesis control signal generation circuit and a data output control circuit. The synthesis control signal generation circuit generates a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command. The data output control circuit outputs data included in a bank group as internal data in response to the synthesis control signal.Type: GrantFiled: November 21, 2018Date of Patent: February 11, 2020Assignee: SK hynix Inc.Inventors: Young Jun Yoon, Hyun Seung Kim
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Publication number: 20200043542Abstract: A semiconductor device may include a first buffer, a second buffer, a divider circuit and an internal signal generation circuit. The first buffer may buffer a first input signal and a second input signal to generate a first data strobe buffering signal and a first data strobe bar buffering signal. The second buffer may generate a second data strobe buffering signal based on the first input signal and a reference xvoltage. The divider circuit may divide the second data strobe buffering signal to generate a divided signal and a divided bar signal. The internal signal generation circuit may be configured to generate a first to fourth data latch timing signals having different phases based on the first data strobe buffering signal, the first data strobe bar buffering signal, the divided signal and the divided buffering signal.Type: ApplicationFiled: October 15, 2019Publication date: February 6, 2020Applicant: SK hynix Inc.Inventors: Sang Kwon LEE, Kwang Soon KIM, Young Hoon KIM, Young Jun YOON, Kyu Dong HWANG