Patents by Inventor Young-Lyong Kim
Young-Lyong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190221520Abstract: A semiconductor package includes a lower chip, an upper chip on the lower chip, and an adhesive layer between the lower chip and the upper chip. The lower chip has first through silicon vias (TSVs) and pads on an upper surface thereof. The pads are connected to the first TSVs, respectively. The upper chip includes bumps on a lower surface thereof. The bumps are bonded to the pads. Vertical centerlines of the bumps are aligned with vertical centerlines of the first TSVs, respectively. The vertical centerlines of the bumps are offset from the vertical centerlines of the pads, respectively, in a peripheral region of the lower chip.Type: ApplicationFiled: August 13, 2018Publication date: July 18, 2019Inventors: YOUNG-LYONG KIM, SEUNG-DUK BAEK
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Publication number: 20190206841Abstract: A semiconductor package includes a first semiconductor chip having a first chip substrate, the first chip substrate having a first upper surface and a first lower surface opposite to each other, a first through-silicon via (TSV), a lower connection pad and a first lower passivation layer on the first lower surface of the first chip substrate, the first lower passivation layer exposing a portion of the lower connection pad, an upper connection pad and a first upper passivation layer on the first upper surface of the first chip substrate, the first upper passivation layer including a first upper inorganic material layer, and a second semiconductor chip connected to the first semiconductor chip, the second semiconductor chip including a second TSV, wherein the first lower passivation layer has a stacked structure of a first lower inorganic material layer and a lower organic material layer.Type: ApplicationFiled: August 21, 2018Publication date: July 4, 2019Inventors: Young Lyong KIM, Seung Duk BAEK
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Publication number: 20190096869Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.Type: ApplicationFiled: November 27, 2018Publication date: March 28, 2019Inventors: Young Lyong KIM, Jin-woo PARK, CHOONGBIN YIM, Younji MIN
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Publication number: 20190013272Abstract: A semiconductor package is provided including a package substrate, a first semiconductor chip on the substrate, with a first surface and a second surface opposite to each other; a plurality of first connection terminals disposed on the first surface contacting an upper surface of the substrate; a second semiconductor chip disposed on the second surface, with a third surface and a fourth surface opposite to each other; a plurality of second connection terminals disposed on the third surface contacting the second surface, wherein an absolute value between a first area, the sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate, and a second area, the sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip, is equal to or less than about 0.3 of the first area.Type: ApplicationFiled: January 13, 2018Publication date: January 10, 2019Inventors: Geol NAM, Young Lyong KIM
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Patent number: 10177131Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.Type: GrantFiled: February 24, 2017Date of Patent: January 8, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Lyong Kim, Jin-woo Park, Choongbin Yim, Younji Min
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Publication number: 20170256511Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.Type: ApplicationFiled: February 24, 2017Publication date: September 7, 2017Inventors: Young Lyong KIM, Jin-woo PARK, CHOONGBIN YIM, Younji MIN
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Patent number: 9570423Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: GrantFiled: December 2, 2015Date of Patent: February 14, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Young-lyong Kim, Ae-nee Jang
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Patent number: 9373574Abstract: Disclosed are semiconductor packages and methods of forming the same. In the semiconductor packages and the methods, a package substrate includes a hole not overlapped with semiconductor chips. Thus, a molding layer may be formed without a void.Type: GrantFiled: July 3, 2013Date of Patent: June 21, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ae-nee Jang, Young Lyong Kim, Jaegwon Jang
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Patent number: 9312213Abstract: A bump structure may include a body portion spaced apart from a pad disposed on a substrate and a first extension extending from a side of the body portion onto the pad. A second extension extends from another side of the body portion.Type: GrantFiled: August 29, 2013Date of Patent: April 12, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Moon Gi Cho, Young Lyong Kim, Sun-Hee Park, Hwan-Sik Lim
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Patent number: 9299631Abstract: According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.Type: GrantFiled: May 23, 2014Date of Patent: March 29, 2016Assignee: Samsung Electronics Co., Ltd.Inventors: Ae-Nee Jang, Young-Lyong Kim
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Publication number: 20160086931Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Chul-yong JANG, Young-lyong KIM, Ae-nee JANG
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Publication number: 20160086924Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: ApplicationFiled: December 2, 2015Publication date: March 24, 2016Inventors: Chul-yong JANG, Young-lyong KIM, Ae-nee JANG
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Patent number: 9281235Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.Type: GrantFiled: February 3, 2015Date of Patent: March 8, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young-lyong Kim, Taehoon Kim, Jongho Lee, Chul-Yong Jang
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Patent number: 9245816Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: GrantFiled: July 10, 2014Date of Patent: January 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Young-lyong Kim, Ae-nee Jang
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Patent number: 9159705Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.Type: GrantFiled: June 13, 2014Date of Patent: October 13, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-yong Jang, Ae-nee Jang, Young-lyong Kim
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Publication number: 20150155199Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.Type: ApplicationFiled: February 3, 2015Publication date: June 4, 2015Inventors: Young Lyong KIM, Taehoon KIM, Jongho LEE, Chul-Yong JANG
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Patent number: 9024448Abstract: A semiconductor package may include a circuit board chip having a through-hole, a semiconductor device mounted on the circuit board chip, and an encapsulant. The encapsulant encapsulates the semiconductor device, fills the through-hole and has an external pattern that is the complement of a mold within which the encapsulant was formed. The external pattern on one side of the package reflects a mold shape that retards the flow of encapsulant material relative to the flow of encapsulant material on the opposite side of the package.Type: GrantFiled: March 5, 2013Date of Patent: May 5, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Gwon Jang, Young-Lyong Kim, Ae-Nee Jang
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Publication number: 20150091149Abstract: According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.Type: ApplicationFiled: May 23, 2014Publication date: April 2, 2015Inventors: Ae-Nee JANG, Young-Lyong KIM
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Patent number: 8970046Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.Type: GrantFiled: July 11, 2012Date of Patent: March 3, 2015Assignee: Samsung Electronics Co., Ltd.Inventors: Young Lyong Kim, Taehoon Kim, Jongho Lee, Chul-Yong Jang
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Publication number: 20150028474Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.Type: ApplicationFiled: July 10, 2014Publication date: January 29, 2015Inventors: Chul-yong JANG, Young-lyong KIM, Ae-nee JANG