Abstract: A method of synchronizing a driving module includes applying a plurality of original data enable (“DE”) signals to a plurality of timing controller of the driving module, respectively, generating a synch DE signal from the driving module based on the earliest signal among the original DE signals, and transferring the synch DE signal to the plurality of timing controllers in a cascade mode.

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract: An integrated circuit device includes an external power supply input configured to be coupled to an external power supply and a digital circuit, such as a clock signal generator circuit, that generates noise at a power supply input thereof. The device further includes a replica load circuit and a power supply circuit coupled to the external power supply input, to a power supply input of the digital circuit and to a power supply input of the replica load circuit. The power supply circuit is configured to selectively couple the external power supply node to the power supply input of the digital circuit responsive to a voltage at the power supply input of the replica load circuit. The replica load circuit may be configured to provide a load that varies responsive to a voltage at the power supply input of the digital circuit.

Abstract: An I2C router system includes an I2C router part, a first slave device and a second slave device. The I2C router part includes a first I2C router configured to output a first I2C signal via a first I2C bus, and a second I2C router configured to output a second I2C signal via a second I2C bus. The first slave device can be configured to receive the first I2C signal via the first I2C bus. The second slave device can be configured to receive the second I2C signal via the second I2C bus.

Abstract: A semiconductor memory device may include a cell array comprising a plurality of memory cells, each memory cell connected to a word line and a bit line, the cell array divided into a plurality of blocks, each block including a plurality of word lines, the plurality of blocks including at least a first defective block; a nonvolatile storage circuit configured to store address information of the first defective block, and to output the address information to an external device; and a fuse circuit configured to cut off an activation of word lines of the first defective block.

Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.

Abstract: In a method of operating a memory device, a command and a first address from a memory controller are received. A read code word including a first set of data corresponding to the first address, a second set of data corresponding to a second address and a read parity data is read from a memory cell array of the memory device. Corrected data are generated by operating error checking and correction (ECC) using an ECC circuit based on the read cord word.

Abstract: A memory device including: a memory cell array including normal memory cells and spare memory cells arranged in rows and columns including normal columns including the normal memory cells and at least one spare column including spare memory cells, a segment match determining circuit configured to compare a segment address with row address information corresponding to a failed segment and to generate a load control signal, and a column match determining circuit configured to compare column address information corresponding to a failed column in response to the load control signal with a column address and to generate a column address replacement control signal, wherein the memory cells connected to fail columns of the fail segment are replaced with memory cells connected to columns of the spare memory cells in response to the column address replacement control signal.

Abstract: A semiconductor memory device is provided which includes a memory cell group and a fuse cell group including at least one fuse cell to store a failed address corresponding to a defective memory cell in the memory cell group; a spare cell group including a spare memory cell configured to replace the defective memory cell included in the memory cell group; a data sensing/selection circuit configured to read data stored in the memory cell group and the spare cell group in response to an activation of the word line; a fuse sense amplifier configured to read the failed address in response to the activation of the word line; and a repair logic circuit configured to control the data sensing/selection circuit in response to the failed address such that the defective memory cell in the memory cell group is replaced by the spare memory cell.

Abstract: A semiconductor memory device includes; a memory cell array comprising a first sub-memory cell array storing first data having a first characteristic and a second sub-memory cell array storing second data having a second characteristic different from the first characteristic, a first peripheral circuit operatively associated with only the first sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the first sub-memory cell array, and a second peripheral circuit operatively associated with only the second sub-memory cell array to execute at least one of a read operation and a write operation directed to a target memory cell of the second sub-memory cell array.

Abstract: Provided is a refresh method of a volatile memory device. The method includes: detecting a number of disturbances that affect a second memory area as the number of accesses to a first memory area is increased; outputting an alert signal from the volatile memory device to an outside of the volatile memory device when the detected number of disturbances reach a reference value; and performing a refresh operation on the second memory area in response to the alert signal.

Abstract: Provided are a memory device and a memory module, which perform both an ECC operation and a redundancy repair operation. The memory device repairs a single-bit error due to a ‘fail’ cell by using an error correction code (ECC) operation, and also repairs the ‘fail’ cell by using a redundancy repair operation when the ‘fail’ cell is not repairable by the ECC operation. The redundancy repair operation includes a data line repair and a block repair. The ECC operation may change a codeword corresponding to data per one unit of memory cells including the ‘fail’ cell, and may also change the size of parity bits regarding the changed codeword.

Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

Abstract: A method of accessing a semiconductor memory is disclosed which includes outputting a row address and an active command to the semiconductor memory; outputting a column address and a read or write command to the semiconductor memory; and outputting a spare access command to the semiconductor memory to access data from a spare memory cell at a timing based on an additive latency of the semiconductor memory. Related devices and systems are also disclosed.

Abstract: A memory device may be provided which includes a memory cell array including a plurality of sub arrays each sub array having a plurality of memory cells connected to bit lines; an address buffer configured to receive a row address and a column address; and a column decoder configured to receive the column address from the address buffer and, for each of the sub arrays, to select a column selection line corresponding to the column address, from among a plurality of column selection lines, based on different offset values applied to the sub arrays, respectively. The selected column selection lines correspond to bit lines having different physical locations, respectively, according to the different offset values.

Abstract: A refresh address generator may include a lookup table including a first portion storing a first group of addresses associated with a first data retention time, and a second portion storing a second group of addresses associated with a second data retention time different from the first data retention time, wherein the addresses of the first portion are more frequently accessed than the addresses of the second portion to refresh the memory cells corresponding to the addresses. Systems and methods may also implement such refresh address generation.

Abstract: In one example embodiment, a memory system includes a memory module and a memory controller. The memory module is configured generate density information of the memory module based on a number of the bad pages of the memory module, the bad pages being pages that have a fault. The memory controller is configured to map a continuous physical address to a dynamic random access memory (dram) address of the memory module based on the density information received from the memory module.

Abstract: In one example embodiment, a memory module includes a plurality of memory devices and a buffer chip configured to manage the plurality of memory device. The buffer chip includes a memory management unit having an error correction unit configured to perform error correction operation on each of the plurality of memory devices. Each of the plurality of memory devices includes at least one spare column that is accessible by the memory management unit, and the memory management unit is configured to correct errors of the plurality of memory devices by selectively using the at least one spare column based on an error correction capability of the error correction unit.

Abstract: A repair control circuit of controlling a repair operation of a semiconductor memory device includes a row matching block and a column matching block. The row matching block stores fail group information indicating one or more fail row groups among a plurality of row groups. The row groups are determined by grouping a plurality of row addresses corresponding to a plurality of wordlines. The row matching block generates a group match signal based on input row address and the fail group information, such that the group match signal indicates the fail row group including the input row address. The column matching block stores fail column addresses of the fail memory cells, and generates a repair control signal based on input column address, the group match signal and the fail column addresses, such that the repair control signal indicates whether the repair operation is executed or not.