Abstract: The present invention relates to a method of selecting a subset of patterns from a design, to a method of performing source and mask optimization, and to a computer program product for performing the method of selecting a subset of patterns from a design. According to certain aspects, the present invention enables coverage of the full design while lowering the computation cost by intelligently selecting a subset of patterns from a design in which the design or a modification of the design is configured to be imaged onto a substrate via a lithographic process. The method of selecting the subset of patterns from a design includes identifying a set of patterns from the design related to the predefined representation of the design. By selecting the subset of patterns according to the method, the selected subset of patterns constitutes a similar predefined representation of the design as the set of patterns.

Abstract: An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect.

Abstract: An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: An optical proximity correction (OPC) based integrated circuit design system and method introduce a variable rule in which rules are specified in terms of multiple correction actions that yield acceptable results. This category of rules provides more degrees of freedom in actual application so that the rule-based OPC tool can intelligently select the proper valid rule that minimizes the OPC complexity or meets other objectives.

Abstract: A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time.

Abstract: A system and method are provided for analyzing layout patterns via simulation using a lithography model to characterize the patterns and generate rules to be used in rule-based optical proximity correction (OPC). The system and method analyze a series of layout patterns conforming to a set of design rules by simulation using a lithography model to obtain a partition of the pattern spaces into one portion that requires only rule-based OPC and another portion that requires model-based OPC. A corresponding hybrid OPC system and method are also introduced that utilize the generated rules to correct an integrated circuit (IC) design layout which reduces the OPC output complexity and improves turnaround time.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: A system and method for integrated circuit design layout processing are disclosed to partition and extract the layout and optimize settings individually for an optimal solution to provide manufacturability enhancement. The integrated circuit design layout system and method are provided for splitting an integrated circuit layout into independent portions or pieces, which can be processed independently and reassembled together, based on prior information about the layout itself, or predefined data processing flow, which are commonly available at the time of processing individual layouts. The integrated circuit design layout system and method split the layout based on hierarchal geometry segregation rules that are derived from the layout data information or data processing flow.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts through generation of hierarchical design rules which capture localized layout requirements. In contrast to conventional techniques which apply global design rules, the disclosed IC design system and method partition the original design layout into a desired level of granularity based on specified layout and integrated circuit properties. At that localized level, the design rules are adjusted appropriately to capture the critical aspects from a manufacturability standpoint. These adjusted design rules are then used to perform localized layout manipulation and mask data conversion.

Abstract: A system and method for integrated circuit design are disclosed to enhance manufacturability of circuit layouts by applying layout processing to handle imperfections such as jogs in integrated circuit design layouts. The layout processing may be applied to jogs in the original integrated circuit design layout or jogs created post-design by process biases, as well as design rule check and Boolean processes or process compensation.

Abstract: A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.

Abstract: A system that performs target-image-based optical proximity correction on masks that are used to generate an integrated circuit is presented. The system operates by first receiving a plurality of masks that are used to expose features on the integrated circuit. Next, the system computes a target image for a target feature defined by the plurality of masks, wherein mask features from different masks define the target image. The system dissects the feature into a plurality of segments, wherein dissecting the mask feature involves using dissection parameters associated with geometric characteristics of the target image, instead of using dissection parameters associated with geometric characteristics of the mask feature. The system then performs an optical proximity correction (OPC) operation on the plurality of masks, wherein the OPC operation uses parameters associated with geometric characteristics of the target image to perform optical proximity correction on the mask features that define the target image.

Abstract: A structure and method are provided for correcting the optical proximity effects on a tri-tone attenuated phase-shifting mask. An attenuated rim, formed by an opaque region and an attenuated phase-shifting region, can be kept at a predetermined width across the mask or for certain types of structures. Typically, the attenuated rim is made as large as possible to maximize the effect of the attenuated phase-shifting region while still preventing the printing of larger portions of the attenuated phase-shifting region during the development process.

Abstract: An exemplary method for modifying at least part of an integrated circuit layout comprises obtaining an integrated circuit device layout, the integrated circuit device being designed using a library of cells, obtaining a modified library of cells, and replacing at least one cell in the integrated circuit device layout with a corresponding modified cell of the modified library to obtain a modified integrated circuit device layout. The modified library includes modified cells corresponding to cells in the library and candidate areas of each modified cell indicating portions of the cell for further processing. At least some of the modified cells have been modified to at least partially compensate for a manufacturing effect.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.

Abstract: Techniques for forming a mask fabrication layout for a physical integrated circuit design layout include correcting the fabrication layout for proximity effects using a proximity effects model. A proximity effects model is executed to produce an initial output. The initial output is based on a first position for a segment in a fabrication layout. The first position is displaced from a corresponding original edge in the original fabrication layout by a distance equal to an initial bias. The model is also executed to produce a second output based on a second position for the segment. The second position is displaced from the corresponding original edge by a distance equal to a second bias. An optimal bias for the segment is determined based on the initial output and the second output. The segment is displaced in the fabrication layout from the corresponding edge based on the optimal bias.