Patents by Inventor Yu-Chia Liu
Yu-Chia Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240147664Abstract: A flow guiding device in an immersion-cooled chassis of a server comprises at least one deflector located above a chip on a mainboard in the chassis, each deflector comprises a first end for mounting to the mainboard above the chip and a second end inclined away from the mainboard. The first end is immersed in coolant, the second end is higher than the first end; the deflector further comprises a hollow part including multiple through holes for interrupting upward movement vapor bubbles generated by the hot chip, which reduces probability of the vapor bubbles escaping from the coolant liquid and the chassis. A liquid-cooled chassis having the flow guiding device is also disclosed.Type: ApplicationFiled: December 30, 2022Publication date: May 2, 2024Inventors: SUNG TSANG, TSUNG-LIN LIU, YU-CHIA TING, CHENG-YI HUANG, CHIA-NAN PAI
-
Publication number: 20240147660Abstract: A manifold for cooling server includes an inlet pipe, an outlet pipe, a plurality of first hole groups, and a plurality of second hole groups. The distance between every two adjacent first hole groups is first distance, the distance between every two adjacent second hole groups is second distance, and the first distance is not equal to the second distance. The first distance is designed for one size of server, and the second distance is designed for another size of server. When changing the size of all servers in the rack, turning manifold 100 to 180 degrees to change the first hole groups 30 to the second hole groups 40 for adapting the severs, which makes the manifold 100 adapt two different sizes of server. A rack and a data center cooling system using the manifold are also disclosed.Type: ApplicationFiled: June 12, 2023Publication date: May 2, 2024Inventors: YU-CHIA TING, TSUNG-LIN LIU
-
Publication number: 20240111210Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (A1) or formula (A2): Zr12O8(OH)14(RCO2)18 ??Formula (A1); or Hf6O4(OH)6(RCO2)10 ??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: May 9, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Pin-Chia LIAO, Ting-An LIN, Ting-An SHIH, Yu-Fang TSENG, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
-
Publication number: 20240112912Abstract: A method of manufacturing a semiconductor device includes the following steps. A photoresist layer is formed over a material layer on a substrate. The photoresist layer has a composition including a solvent and a first photo-active compound dissolved in the solvent. The first photo-active compound is represented by the following formula (Al) or formula (A2): Zr12O8(OH)14(RCO2)18??Formula (A1); or Hf6O4(OH)6(RCO2)10??Formula (A2). R in the formula (A1) and R in the formula (A2) each include one of the following formulae (1) to (6): The photoresist layer is patterned. The material layer is etched using the photoresist layer as an etch mask.Type: ApplicationFiled: July 28, 2023Publication date: April 4, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Jui-Hsiung LIU, Yu-Fang TSENG, Pin-Chia LIAO, Burn Jeng LIN, Tsai-Sheng GAU, Po-Hsiung CHEN, Po-Wen CHIU
-
Publication number: 20240113071Abstract: An integrated circuit package including electrically floating metal lines and a method of forming are provided. The integrated circuit package may include integrated circuit dies, an encapsulant around the integrated circuit dies, a redistribution structure on the encapsulant, a first electrically floating metal line disposed on the redistribution structure, a first electrical component connected to the redistribution structure, and an underfill between the first electrical component and the redistribution structure. A first opening in the underfill may expose a top surface of the first electrically floating metal line.Type: ApplicationFiled: January 5, 2023Publication date: April 4, 2024Inventors: Chung-Shi Liu, Mao-Yen Chang, Yu-Chia Lai, Kuo-Lung Pan, Hao-Yi Tsai, Ching-Hua Hsieh, Hsiu-Jen Lin, Po-Yuan Teng, Cheng-Chieh Wu, Jen-Chun Liao
-
Publication number: 20240105795Abstract: A method for fabricating semiconductor devices is disclosed. The method includes forming a gate trench over a semiconductor channel, the gate trench being surrounded by gate spacers. The method includes sequentially depositing a work function metal, a glue metal, and an electrode metal in the gate trench. The method includes etching respective portions of the electrode metal and the glue metal to form a gate electrode above a metal gate structure. The metal gate structure includes a remaining portion of the work function metal and the gate electrode includes a remaining portion of the electrode metal. The gate electrode has an upper surface extending away from a top surface of the metal gate structure.Type: ApplicationFiled: February 16, 2023Publication date: March 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-Ye Liu, Jih-Sheng Yang, Yu-Hsien Lin, Ryan Chia-Jen Chen
-
Publication number: 20230278856Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.Type: ApplicationFiled: May 11, 2023Publication date: September 7, 2023Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
-
Patent number: 11667517Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.Type: GrantFiled: June 22, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
-
Patent number: 11312623Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.Type: GrantFiled: July 31, 2020Date of Patent: April 26, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
-
Publication number: 20210070429Abstract: The present invention relates to a free propeller assembly structure and an aircraft structure has the free propeller assembly. The free propeller assembly structure has at least one free propeller assembly. Each of the at least one free propeller assembly has a circular shaft, a main rotor, a signal transmitting device, and a rotor blade assembly. The main rotor has a shaft hole and multiple blade mounting structures radially disposed. Each blade mounting structure is provided with a positioning recess for mounting a driving motor in each positioning recess. The signal transmitting device includes multiple signal transmitters that are able to transmit interpretable electronic signals or photonic signals. The rotor blade assembly includes at least two rotor blades.Type: ApplicationFiled: September 25, 2020Publication date: March 11, 2021Inventors: Bao-Shen Liu, Yu-Chia Liu
-
Publication number: 20200361767Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.Type: ApplicationFiled: July 31, 2020Publication date: November 19, 2020Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
-
Publication number: 20200317506Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.Type: ApplicationFiled: June 22, 2020Publication date: October 8, 2020Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
-
Patent number: 10752497Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.Type: GrantFiled: December 6, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
-
Patent number: 10689247Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.Type: GrantFiled: January 2, 2018Date of Patent: June 23, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
-
Patent number: 10494252Abstract: The present disclosure provides a CMOS MEMS device. The CMOS MEMS device includes a first substrate, a second substrate, a first polysilicon and a second polysilicon. The second substrate includes a movable part and is located over the first substrate. The first polysilicon penetrates the second substrate and is adjacent to a first side of the movable part of the second substrate. The second polysilicon penetrates the second substrate and is adjacent to a second side of the movable part of the second substrate.Type: GrantFiled: September 22, 2015Date of Patent: December 3, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng
-
Patent number: 10358339Abstract: The invention provides a micro-electro-mechanical device which is manufactured by a CMOS manufacturing process. The micro-electro-mechanical device includes a stationary unit, a movable unit, and a connecting member. The stationary unit includes a first capacitive sensing region and a fixed structure region. The movable unit includes a second capacitive sensing region and a proof mass, wherein the first capacitive sensing region and the second capacitive sensing region form a capacitor, and the proof mass region consists of a single material. The connecting member is for connecting the movable unit in a way to allow a relative movement of the movable unit with respect to the stationary unit.Type: GrantFiled: March 6, 2018Date of Patent: July 23, 2019Assignee: PIXART IMAGING INCORPORATIONInventors: Ming-Han Tsai, Yu-Chia Liu, Wei-Leun Fang
-
Patent number: 10273144Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The device substrate includes a first trench and a second trench. A first MEMS device is disposed over the first trench and a second MEMS device is disposed over the second trench. A first stopper is raised from a first trench bottom surface of the first trench but below a top surface of the device substrate and a second stopper is raised from a second trench bottom surface of the second trench but below the top surface of the device substrate. A first depth of the first trench is greater than a second depth of the second trench.Type: GrantFiled: June 19, 2017Date of Patent: April 30, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Kuei-Sung Chang, Jung-Huei Peng
-
Patent number: 10273148Abstract: Some embodiments of the present disclosure provide a microelectromechanical systems (MEMS). The MEMS includes a semiconductive block. The semiconductive block includes a protruding structure. The protruding structure includes a bottom surface. The semiconductive block includes a sensing structure. A semiconductive substrate includes a conductive region. The conductive region includes a first surface under the sensing structure. The first surface is substantially coplanar with the bottom surface. A dielectric region includes a second surface not disposed over the first surface.Type: GrantFiled: August 14, 2015Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chun-Wen Cheng, Jung-Huei Peng, Chia-Hua Chu, Nien-Tsung Tsai, Yao-Te Huang, Li-Min Hung, Yu-Chia Liu
-
Publication number: 20190112183Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.Type: ApplicationFiled: December 6, 2018Publication date: April 18, 2019Inventors: Yu-Chia Liu, Chia-Hua Chu, Chun-Wen Cheng, Jung-Huei Peng
-
Patent number: 10202278Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a cavity disposed in a substrate and enclosed by a first surface and a second surface opposite to the first surface. The semiconductor structure also includes a first electrode pair having a first electrode on the first surface and a second electrode on the second surface. The first electrode pair is configured to measure a first spacing between the first surface and the second surface. The semiconductor structure further includes a second electrode pair having a third electrode on the first surface and a fourth electrode on the second surface. The second electrode pair is configured to measure a second spacing between the first surface and the second surface.Type: GrantFiled: September 2, 2016Date of Patent: February 12, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jung-Huei Peng, Yi-Chien Wu, Yu-Chia Liu, Chun-Wen Cheng