Patents by Inventor Yu Hasegawa
Yu Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8941237Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.Type: GrantFiled: June 18, 2013Date of Patent: January 27, 2015Assignee: PS4 Luxco S.A.R.L.Inventors: Yu Hasegawa, Mitsuaki Katagiri
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Patent number: 8742499Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: GrantFiled: October 29, 2009Date of Patent: June 3, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Shizuki Nakajima, Hiroyuki Nagai, Yuji Shirai, Hirokazu Nakajima, Chushiro Kusano, Yu Hasegawa, Chiko Yorita, Yasuo Osone
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Publication number: 20140070765Abstract: A charging apparatus is provided that avoids a reduction in the strength of radio waves or a magnetic field used by a charging target device having a wireless communication function and reduces an influence on the radio waves or magnetic field. In this apparatus, position detection section (201) detects a position of power reception coil (251) of charging target device (150) placed on charging table (101). Power transmission coil (208) is made close to power reception coil (251) and transmits electric power. Coil moving mechanism (207) brings power transmission coil (208) close to the position of power reception coil (251) that is detected by position detection section (201).Type: ApplicationFiled: February 13, 2013Publication date: March 13, 2014Applicant: PANASONIC CORPORATIONInventors: Yu Hasegawa, Masanobu Kanaya, Yukio Iijima, Kazunori Yamada
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Publication number: 20140035166Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: October 9, 2013Publication date: February 6, 2014Applicant: Elpida Memory, Inc.Inventors: Yu HASEGAWA, Mitsuaki Katagiri, Satoshi Isa, Ken Iwakura, Dai Sasaki
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Patent number: 8581417Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: January 14, 2010Date of Patent: November 12, 2013Assignee: Elpida Memory, Inc.Inventors: Yu Hasegawa, Mitsuaki Katagiri, Satoshi Isa, Ken Iwakura, Dai Sasaki
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Publication number: 20130277835Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.Type: ApplicationFiled: June 18, 2013Publication date: October 24, 2013Inventors: Yu HASEGAWA, Mitsuaki KATAGIRI
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Patent number: 8487433Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.Type: GrantFiled: July 27, 2011Date of Patent: July 16, 2013Assignee: Elpida Memory, Inc.Inventors: Yu Hasegawa, Mitsuaki Katagiri
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Publication number: 20120292772Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.Type: ApplicationFiled: July 30, 2012Publication date: November 22, 2012Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
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Publication number: 20120061826Abstract: A device includes a substrate, a semiconductor chip, first and second pads, and a first wiring layer. The substrate includes first and second surfaces. The semiconductor chip includes third and fourth surfaces. The third surface faces toward the first surface. The first and second pads are provided on the third surface. The first and second pads are connected to each other. The first wiring layer is provided on the second surface of the substrate. The first wiring layer is connected to the first pad.Type: ApplicationFiled: July 27, 2011Publication date: March 15, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Yu HASEGAWA, Mitsuaki KATAGIRI
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Publication number: 20110084395Abstract: A semiconductor device includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The package substrate has internal terminals connected to the semiconductor chip, front surface wirings connected to the internal terminals, rear surface wirings connected to external electrodes, and contacts connecting the front surface wiring and rear surface wiring. Out of the plurality of contact, some contacts included in the wirings for signal transmission are disposed near the internal terminals. Thus, a signal led out from the semiconductor chip is immediately taken away from the chip mounting surface of the package substrate. This reduces the floating capacitance between the wirings on the package substrate and chip, thereby improving the signal quality.Type: ApplicationFiled: October 5, 2010Publication date: April 14, 2011Applicant: ELPIDA MEMORY, INC.Inventors: Hiromasa Takeda, Satoshi Isa, Mitsuaki Katagiri, Ken Iwakura, Yu Hasegawa
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Publication number: 20100193933Abstract: In a semiconductor device of the present invention, a second semiconductor chip is stacked on a first semiconductor chip having a plurality of bonding pads in its central region, with a bonding layer interposed therebetween. A plurality of wires respectively connected to the plurality of bonding pads of the first semiconductor chip are led out to the outside over a peripheral edge of the first semiconductor chip by passing through a space between the first and second semiconductor chips. A retaining member for retaining at least a subset of the plurality of wires is provided in a region on the first semiconductor chip including a middle point between the bonding pads and the peripheral edge of the first semiconductor chip by using a material different from the bonding layer so that the subset of the wires is positioned generally at a center of the spacing between the first semiconductor chip and the second semiconductor chip.Type: ApplicationFiled: January 14, 2010Publication date: August 5, 2010Inventors: Yu HASEGAWA, Mitsuaki KATAGIRI, Satoshi ISA, Ken IWAKURA, Dai SASAKI
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Publication number: 20100172116Abstract: A shielded electronic component including a wiring board, at least one semiconductor chip mounted on a main surface of the wiring board, a sealant which seals the whole of an upper surface of the wiring board, and a nickel (Ni) plating film formed on an upper surface of the sealant is provided. The Ni plating film is formed on a palladium (Pd) pretreatment layer formed on the upper surface of the sealant with using high-pressure CO2 in a state of protecting a back surface of the wiring board, and is electrically connected with an end portion of a ground wiring layer of the wiring board or a ground (GND) connection through-hole connected with the end portion of the ground wiring layer.Type: ApplicationFiled: November 5, 2009Publication date: July 8, 2010Inventors: Chiko Yorita, Yoshihide Yamaguchi, Yuji Shirai, Yu Hasegawa
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Publication number: 20100109052Abstract: In a semiconductor chip in which LDMOSFET elements for power amplifier circuits used for a power amplifier module are formed, a source bump electrode is disposed on an LDMOSFET formation region in which a plurality of source regions, a plurality of drain regions and a plurality of gate electrodes for the LDMOSFET elements are formed. The source bump electrode is formed on a source pad mainly made of aluminum via a source conductor layer which is thicker than the source pad and mainly made of copper. No resin film is interposed between the source bump electrode and the source conductor layer.Type: ApplicationFiled: October 29, 2009Publication date: May 6, 2010Inventors: Shizuki NAKAJIMA, Hiroyuki NAGAI, Yuji SHIRAI, Hirokazu NAKEJIMA, Chushiro KUSANO, Yu HASEGAWA, Chiko YORITA, Yasuo OSONE
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Patent number: 7656030Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: GrantFiled: January 10, 2007Date of Patent: February 2, 2010Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
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Publication number: 20090310062Abstract: To provide a linear light source device (1) arranged on a lateral surface of a light guide plate, comprising: a plurality of linear light source assemblies (3) each including an elongated substrate and a plurality of light emitting elements linearly mounted on one of main surfaces of the sub substrate; and a main substrate (2) having mounted thereon the linear light source assemblies (3). With this structure, even if the linear light source device (1) is elongated, luminance unevenness is hardly caused in planar light emitting devices and liquid crystal display devices.Type: ApplicationFiled: June 23, 2006Publication date: December 17, 2009Inventors: Yoshihiko Chosa, Hiroshi Uchida, Tetsuya Fukudome, Hisakazu Kawahara, Toshiro Horiuchi, Yu Hasegawa, Kouji Hidaka, Hiroshi Yamaguchi
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Patent number: 7554193Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: GrantFiled: August 16, 2006Date of Patent: June 30, 2009Assignee: Renesas Technology Corp.Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
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Publication number: 20070176298Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.Type: ApplicationFiled: January 10, 2007Publication date: August 2, 2007Applicants: Hitachi, Ltd., Renesas Technology Corp.Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
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Publication number: 20070040255Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.Type: ApplicationFiled: August 16, 2006Publication date: February 22, 2007Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
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Patent number: 6118411Abstract: A closed loop is formed by loop antenna elements which equivalently function as inductance, a capacitor inserted in such a manner as to divide the loop antenna into the loop antenna elements, and an impedance-matching dividing element for tuning the antenna and establishing matching with a high-frequency circuit side. A subsidiary substrate with the capacitor mounted thereon is fixedly installed by a retaining pawl of an antenna holder, and is connected to the loop antenna elements by being soldered thereto at a pair of lands on the subsidiary substrate. As a result, it is possible to improve the effective gain of the antenna and effectively utilize the substrate space.Type: GrantFiled: April 19, 1999Date of Patent: September 12, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yu Hasegawa, Nobutaka Mochizuki, Kenichi Nishikawa, Kazuhiro Ikeda, Syuuichi Sugawara
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Patent number: 5650697Abstract: The improved motor drive unit includes a zero-crossing voltage detector circuit composed of components (7) to (12) for detecting whether the voltage from an AC power supply (1) is zero-crossing and a switching circuit for performing on-off control by means of a thyristor 27 so as to switch between energization and de-energization of the AC power supply to a motor (2) and controls the speed of the motor by changing the ratio between the times of energization and de-energization of the AC power supply to the motor. The start of energization coincides with the zero-crossing of the AC power supply voltage whereas the timing of end of energization coincides with the zero-crossing of an energization current by means of the thyristor and wherein the energization time is fixed at a value either equal to or twice the power supply period whereas the de-energization time is varied in units that are integral multiples of one half the power supply period.Type: GrantFiled: June 7, 1995Date of Patent: July 22, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Akihiko Imagi, Yoshio Yoshikuwa, Takuo Akiyama, Norikazu Ishikawa, Tatsunao Hayashida, Yu Hasegawa, Kenshi Kawagishi, Kazuyuki Mitsushima, Haruhiko Ishida, Hidekazu Totsuka