Abstract: A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature of between about 150° C. and about 230° C.

Abstract: A package includes a die and a redistribution structure. The die has an active surface and is wrapped around by an encapsulant. The redistribution structure disposed on the active surface of the die and located above the encapsulant, wherein the redistribution structure comprises a conductive via connected with the die, a routing pattern located above and connected with the conductive via, and a seal ring structure, the seal ring structure includes a first seal ring element and a second seal ring element located above and connected with the first seal ring element, wherein the second seal ring element includes a seed layer sandwiched between the first seal ring element and the second seal ring element, and a top surface of the first seal ring element is substantially coplanar with a top surface of the conductive via.

Abstract: A composition for a sacrificial film includes a polymer, a solvent, and a plasticize compound having an aromatic ring structure. A package includes a die, through insulating vias (TIV), an encapsulant, and a redistribution structure. The die includes a sensing component. The TIVs surround the die. The encapsulant laterally encapsulates the die and the TIVs. The redistribution structure is over the die, the TIVs, and the encapsulant. The redistribution structure has an opening exposing the sensing component of the die. A top surface of the redistribution structure is slanted.

Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.

Abstract: A semiconductor package includes a semiconductor die and a redistribution structure. The semiconductor die is laterally surrounded by a molding compound, and the semiconductor die has a conductive pillar and a complex compound sheath sandwiched between the conductive pillar and the molding compound. The redistribution structure is electrically connected with the semiconductor die and comprises a first via portion at a first side of the redistribution structure and a second via portion at a second side of the redistribution structure, and a base angle of the second via portion is greater than a base angle of the first via portion.

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: In an embodiment, a device includes: a semiconductor die including a semiconductor material; a through via adjacent the semiconductor die, the through via including a metal; an encapsulant around the through via and the semiconductor die, the encapsulant including a polymer resin; and an adhesion layer between the encapsulant and the through via, the adhesion layer including an adhesive compound having an aromatic compound and an amino group, the amino group bonded to the polymer resin of the encapsulant, the aromatic compound bonded to the metal of the through via, the aromatic compound being chemically inert to the semiconductor material of the semiconductor die.

Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.

Abstract: An optical interconnect structure including a base substrate, an optical waveguide, a first reflector, a second reflector, a dielectric layer, a first lens, and a second lens is provided. The optical waveguide is embedded in the base substrate. The optical waveguide includes a first end portion and a second end portion opposite to the first end portion. The first reflector is disposed between the base substrate and the first end portion of the optical waveguide. The second reflector is disposed between the base substrate and the second end portion of the optical waveguide. The dielectric layer covers the base substrate and the optical waveguide. The first lens is disposed on the dielectric layer and located above the first end portion of the optical waveguide. The second lens is disposed on the dielectric layer and located above the second end portion of the optical waveguide.

Abstract: A semiconductor package includes a semiconductor die including a sensing component, an encapsulant laterally covering the semiconductor die, a through insulator via (TIV) and a dummy TIV penetrating through the encapsulant, a patterned dielectric layer disposed on the top surfaces of the encapsulant and the semiconductor die, a conductive pattern disposed on and inserted into the patterned dielectric layer to be in contact with the TIV and the semiconductor die, and a first dummy conductive pattern disposed on the patterned dielectric layer and connected to the dummy TIV. The top surface of the encapsulant is above and rougher than a top surface of the semiconductor die, and the sensing component is accessibly exposed by the patterned dielectric layer.

Abstract: A package structure includes a plurality of semiconductor die, an insulating encapsulant and a redistribution layer. Each of the plurality of semiconductor dies includes a semiconductor substrate, conductive pads disposed on the semiconductor substrate, conductive posts disposed on the conductive pads, and at least one alignment mark located on the semiconductor substrate. The insulating encapsulant is encapsulating the plurality of semiconductor dies. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the plurality of semiconductor dies.

Abstract: A package structure includes a first redistribution layer, a semiconductor die and a second redistribution layer. The first redistribution layer includes a first dielectric layer, first conductive elements, second conductive elements, a top dielectric layer and an auxiliary dielectric portion. The first conductive elements and the second conductive elements are disposed on the first dielectric layer with a first pattern density and a second pattern density respectively. The top dielectric layer is disposed on the first dielectric layer and covering a top surface of the second conductive elements. The auxiliary dielectric portion is disposed in between the first dielectric layer and the top dielectric layer, and covering a top surface of the first conductive elements. The semiconductor die is disposed on the first redistribution layer. The second redistribution layer is disposed on the semiconductor die, and electrically connected to the semiconductor die and the first redistribution layer.

Abstract: A method includes forming a reconstructed wafer including encapsulating a device die in an encapsulant, forming a dielectric layer over the device die and the encapsulant, forming a plurality of redistribution lines extending into the dielectric layer to electrically couple to the device die, and forming a metal ring in a common process for forming the plurality of redistribution lines. The metal ring encircles the plurality of redistribution lines, and the metal ring extends into scribe lines of the reconstructed wafer. A die-saw process is performed along scribe lines of the reconstructed wafer to separate a package from the reconstructed wafer. The package includes the device die and at least a portion of the metal ring.

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A method of manufacturing a semiconductor device includes placing a polymer raw material mixture over a substrate. The polymer raw material may include a polymer precursor, a photosensitizer, and an additive. The polymer raw material mixture is exposed to radiation to form a dielectric layer and cured at a temperature of between about 150° C. and about 230° C.

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

Abstract: A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A chip package includes a semiconductor die laterally encapsulating by an insulating encapsulant, a first dielectric portion, conductive vias, conductive traces and a second dielectric portion. The first dielectric portion covers the semiconductor die and the encapsulant. The conductive vias penetrate through the first dielectric portion and electrically connected to the semiconductor die. The conductive traces are disposed on the first dielectric portion. The second dielectric portion is disposed on the first dielectric portion and covering the conductive traces, wherein a first minimum lateral width of a conductive trace among the conductive traces is smaller than a second minimum lateral width of a conductive via among the conductive vias. A method of forming the chip package is also provided.

Abstract: A manufacturing method of a semiconductor package includes the following steps. A supporting layer is formed over a redistribution structure. A first planarization process is performed over the supporting layer. A lower dielectric layer is formed over the supporting layer, wherein the lower dielectric layer includes a concave exposing a device mounting region of the supporting layer. A first sacrificial layer is formed over the supporting layer, wherein the sacrificial layer filling the concave. A second planarization process is performed over the lower dielectric layer and the first sacrificial layer. A transition waveguide provided over the lower dielectric layer. The first sacrificial layer is removed. A semiconductor device is mounted over the device mounting region, wherein the semiconductor device includes a device waveguide is optically coupled to the transition waveguide.