Abstract: The invention relates to processes for preparing benzoprostacyclin analogues and intermediates prepared from the process, and the benzoprostacyclin analogues prepared therefrom. The invention also relates to cyclopentenone intermediates in racemic or optically active form.

Abstract: Nano- and micro-particles (NMP) can be formed from an oil/water emulsion. The emulsion is made by mixing a liquid solvent, at least one surfactant, a particle-forming compound, and at least curing agent. If desired, pH control agents and viscosity enhancers can be added to the liquid solvent. The particle-forming compound and the curing agents are mixed together and form the oil phase in the emulsion and after curing, the particles are formed. The nano- and micro-particles can be used as proppant to enhance the conductivity of nano- and microfractures and fluid-loss-control additive for hydraulic fracturing operations.

Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.

Abstract: A precharge method for a data driver includes steps of: outputting a display data to a plurality of output terminals of the data driver; outputting a second precharge voltage to an output terminal among the plurality of output terminals prior to outputting the display data to the output terminal, to precharge the output terminal to a voltage level closer to an output voltage; and outputting a first precharge voltage to the output terminal prior to outputting the second precharge voltage. The first precharge voltage provides a faster voltage transition on the output terminal than the second precharge voltage.

Abstract: A transient voltage suppression device includes at least one P-type lightly-doped structure and at least one electrostatic discharge structure. The electrostatic discharge structure includes an N-type lightly-doped well, an N-type well, a first P-type heavily-doped area, and a first N-type heavily-doped area. The N-type lightly-doped well is formed in the P-type lightly-doped structure. The N-type well is formed in the N-type lightly-doped well. The doping concentration of the N-type lightly-doped well is less than that of the N-type well. The first P-type heavily-doped area is formed in the N-type well. The first N-type heavily-doped area is formed in the P-type lightly-doped structure.

Abstract: A packet sorting and reassembly circuit module, including a header parser, an information processing circuit, at least one state tracking and reassembly circuit, and an output arbiter, is provided. The header parser is configured to analyze multiple first packet segments to obtain header information corresponding to a first network packet, wherein the first network packet is transmitted based on a transmission control protocol (TCP) communication protocol. The information processing circuit is configured to transmit the first packet segments and sideband information corresponding to the first packet segments to a first state tracking and reassembly circuit among the at least one state tracking and reassembly circuit according to the header information. The first state tracking and reassembly circuit is configured to reassemble and sort the first packet segments according to the sideband information. The output arbiter is configured to output the first packet segments according to a sorting result.

Abstract: A computer-implemented method, a computer system, and computer program product for associating security events. The method includes obtaining a result of implementation of one or more Locality-Sensitive Hashing (LSH) functions to feature data of a first event detected by a first device. The method also includes mapping the result to one or more positions in a data structure. In response to data elements of the one or more positions indicating first information associating with the one or more positions exists in a storage, the method includes obtaining the first information from the storage. The method further includes sending the first information to the first device.

Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.

Abstract: A case tampering detection device, used for a computer system covered with a computer case, includes at least one detector for detecting whether the computer case is opened and generating a detection result; a storage unit; a microcontroller unit, coupled to the storage unit, for generating a case tampering event and storing the case tampering event in the microcontroller unit or the storage unit when being powered; and a power supply unit, coupled to the at least one detector, for receiving the detection result, and supplying power to the microcontroller unit when the detection result indicates that the computer case is opened.

Abstract: A water quality detection device including a detection tank, a sensor, the cleaner and a processor is provided. The sensor is disposed on the detection tank and is configured to sense a to-be-detected liquid within the detection tank. The cleaner is configured to clean the sensor. The processor is electrically connected to the sensor and the cleaner and is configured to: execute an initialization procedure, which includes driving the sensor to sense the to-be-detected liquid to obtain a number of initial sensing values and calculating a threshold value according to the initial sensing values; drive the sensor to sense the to-be-detected liquid to obtain a sensing value of the to-be-detected liquid, and determine whether the sensing value of the to-be-detected liquid reaches the threshold value; drive the cleaner to operate when the sensing value of the to-be-detected liquid reaches the threshold value.

Abstract: Methods and systems for detecting systemwide service issues by using anomaly localization. In an example, a method includes receiving time-series monitoring data for multiple services, the time-series monitoring data including multiple dimensions and an error metric; for the monitoring data from each service, evaluating scopes within the monitoring data based on an objective function for a time-series of the error metric to identify at least one anomalous scope, each scope including at least one dimension and a value for the dimension; based on evaluating the scopes, generating a ranked list of scopes for each service based on objective function scores for the scopes; correlating the ranked lists of scopes across the multiple services to identify a cross-service anomaly; and generating an alert for the services based on the cross-service anomaly, the alert indicating at least one scope as a potential root cause for the cross-service anomaly.

Abstract: A manifold for cooling server includes an inlet pipe, an outlet pipe, a plurality of first hole groups, and a plurality of second hole groups. The distance between every two adjacent first hole groups is first distance, the distance between every two adjacent second hole groups is second distance, and the first distance is not equal to the second distance. The first distance is designed for one size of server, and the second distance is designed for another size of server. When changing the size of all servers in the rack, turning manifold 100 to 180 degrees to change the first hole groups 30 to the second hole groups 40 for adapting the severs, which makes the manifold 100 adapt two different sizes of server. A rack and a data center cooling system using the manifold are also disclosed.

Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.

Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: A method and apparatus for aiming at a virtual object in a virtual environment, which: displays a user interface (UI), the UI including a picture of a virtual environment including a first virtual object and at least one second virtual object located in the virtual environment; displays a dot aiming indicator in the virtual environment in response to an aiming instruction, the dot aiming indicator being used for indicating an aiming point selected by an aiming operation on a ground plane of the virtual environment; and controls the first virtual object to aim at a target virtual object, which is a virtual object selected from a second virtual object in a target selection range which is a selection range determined by using the aiming point as a benchmark.

Abstract: A display device includes a panel, a conductive layer, a first color filter array and a second color filter array. The panel has a display surface and multiple sub-pixel regions where the multiple sub-pixel regions and the conductive layer are on this display surface. The first color filter array including multiple first color filter elements is disposed on the conductive layer while the second color filter array including multiple second color filter elements is disposed on the first color filter array. One first overlaid region and one second overlaid region are defined by the orthogonal projections of the color filter elements within one of the sub-pixel regions. In one sub-pixel region, a section of the first overlaid region does not overlap a section of the second overlaid region.

Abstract: A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Abstract: In some aspects, the techniques described herein relate to a quantum method for solving a second-order cone program (SOCP) instance, the method including: defining a Newton system for the SOCP instance by constructing matrix G and vector h based on the SOCP instance; preconditioning matrix G and vector h via row normalization to reduce a condition number of matrix G; iteratively determining u until a predetermined iteration condition is met, the iterations including: causing a quantum computing system to apply matrix G and vector h to a quantum linear system solver (QLSS) to generate a quantum state; causing the quantum computing system to perform quantum state tomography on the quantum state; and updating a value of u based on a current value of u and the output of the quantum state tomography; and determining a solution to the SOCP instance based on the updated value of u.

Abstract: A memory device includes a plurality of memory cells disposed over a substrate and formed as an array that has a plurality of rows and a plurality of columns. Each of the plurality of memory cells includes a plurality of transistors. A first subset of the plurality of memory cells, that are disposed in first neighboring ones of the plurality of rows, are physically coupled to a corresponding one of a plurality of second interconnect structures that carries a supply voltage through a corresponding one of a plurality of first interconnect structures. The plurality of first interconnect structures extend along a first lateral direction in parallel with a lengthwise direction of a channel of each of the transistors of the memory cells, and the plurality of second interconnect structures, disposed above the plurality of first interconnect structures, extend along a second lateral direction perpendicular to the first lateral direction.