Patents by Inventor Yu-Ting Chen
Yu-Ting Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230317497Abstract: A display apparatus includes a carrier base, a pixel driving circuit, an insulating layer, a pad group, a light-emitting element, and a first fixing element. The pixel driving circuit is disposed on the carrier base. The insulating layer is disposed on the pixel driving circuit. The pad group is disposed on the insulating layer and is electrically connected to the pixel driving circuit. The light-emitting element is electrically connected to the pad group. The first fixing element is disposed on the insulating layer and at least located on two opposite sides of the pad group. In a direction perpendicular to the carrier base, the light-emitting element has a height HLED, the first fixing element has a height HPS1, a pad of the pad group has a thickness HPAD. HLED, HPS1, and HPAD satisfy: H L E D ? _ H P S 1 ? _ 1.4 ? H L E D + H P A D . Or, HLED, HPS1, and HPAD satisfy: H L E D + 90 ? m ? _ H P S 1 ? _ 1.4 ? H L E D + H P A D + 90 ? m .Type: ApplicationFiled: December 7, 2022Publication date: October 5, 2023Applicant: AUO CorporationInventors: Bo-Chen Chen, Yu Ting Chen
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Patent number: 11758740Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.Type: GrantFiled: April 7, 2021Date of Patent: September 12, 2023Assignee: Winbond Electronics Corp.Inventors: Chang-Tsung Pai, Chiung-Lin Hsu, Yu-Ting Chen, Ming-Che Lin, Chi-Ching Liu
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Publication number: 20230259579Abstract: Methods and systems relating to reducing the number of computations required to execute an artificial neural network (ANN) are disclosed herein. A disclosed method includes: generating a summary of a set of data which is an input for a composite computation; executing a simplified composite computation, using the summary, to produce a simplified output; and executing a second simplified composite computation, using the simplified output, to produce a second simplified output which is a predictor. The second simplified composite computation is a simplification of a second composite computation. The composite computations are both part of a complex computation for the directed graph. The second composite computation depends on the composite computation in the directed graph. The method further includes suppressing, while executing the complex computation, a set of component computations from the second composite computation. The set of component computations are selected for suppression based on the predictor.Type: ApplicationFiled: January 31, 2022Publication date: August 17, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Patent number: 11709662Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: GrantFiled: November 5, 2021Date of Patent: July 25, 2023Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Patent number: 11693639Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: GrantFiled: November 5, 2021Date of Patent: July 4, 2023Assignee: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230203233Abstract: An aqueous polyurethane dispersion and a textile are provided. The aqueous polyurethane dispersion includes water and a bio-based polyurethane. The bio-based polyurethane includes bio-based polyester polyol, hydrophilic polyol, isocyanate, and hydrophilic compound. A weight ratio of the bio-based polyester polyol to the hydrophilic polyol is 2.7:1 to 5.3:1.Type: ApplicationFiled: December 29, 2021Publication date: June 29, 2023Applicant: Industrial Technology Research InstituteInventors: Albert Wan, Yu-Ting Chen, Min-Yan Dong, Jing-Wen Tang
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Publication number: 20230196124Abstract: Methods and systems relating to reducing the number of computations required to execute an artificial neural network (ANN) are disclosed herein. The methods include a computer-implemented method conducted during an execution of an ANN. The method includes generating a set of execution data, generating a summary of a set of neural network data of the ANN, generating a summary of a set of execution data of the execution of the ANN, generating a prediction using the summary of the set of neural network data and the summary of the set of execution data, and executing a composite computation. The composite computation is required for the execution of the ANN. The method also includes suppressing a set of component computations of the composite computation. The set of suppressed component computations is at least partly determined by the prediction.Type: ApplicationFiled: December 22, 2021Publication date: June 22, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Akhmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230165504Abstract: An electrocardiogram converting device includes a casing, a first connector, a chest lead connection module, and a limb lead connection module. The casing includes a first surface, a second surface, and a third surface. The first connector is installed on the first surface of the casing, the chest lead connection module is installed on the second surface of the casing, and the limb lead connection module is installed on the third surface of the casing. In addition, the second surface is perpendicular to the third surface, and the first surface is parallel to the third surface, so as to reduce a length and a volume of the electrocardiogram converting device and improve the convenience of electrocardiogram measurement.Type: ApplicationFiled: November 30, 2022Publication date: June 1, 2023Inventors: Jui-Chung CHANG, Yu-Ting CHEN, Ying-Lung CHENG
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Publication number: 20230146541Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Ahmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Publication number: 20230143538Abstract: Methods and systems relating to the field of parallel computing are disclosed herein. The methods and systems disclosed include approaches for sparsity uniformity enforcement for a set of computational nodes which are used to execute a complex computation. A disclosed method includes determining a sparsity distribution in a set of operand data, and generating, using a compiler, a set of instructions for executing, using the set of operand data and a set of processing cores, a complex computation. Alternatively, the method includes altering the operand data. The method also includes distributing the set of operand data to the set of processing cores for use in executing the complex computation in accordance with the set of instructions. Either the altering is conducted to, or the compiler is programmed to, balance the sparsity distribution among the set of processing cores.Type: ApplicationFiled: November 5, 2021Publication date: May 11, 2023Applicant: Tenstorrent Inc.Inventors: Ljubisa Bajic, Davor Capalija, Yu Ting Chen, Andrew Grebenisan, Hassan Farooq, Ahmed Rakhmati, Stephen Chin, Vladimir Blagojevic, Almeet Bhullar, Jasmina Vasiljevic
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Patent number: 11644710Abstract: A display panel is provided. The display panel includes a sensing region. The display panel includes a capping substrate, a light shielding layer, and a transparent material. The light shielding layer is disposed under the capping substrate. The light shielding layer includes a plurality of holes. The transparent material is disposed under the light shielding layer. The plurality of holes and the transparent material correspond to the sensing region.Type: GrantFiled: June 14, 2022Date of Patent: May 9, 2023Assignee: INNOLUX CORPORATIONInventors: Yun-Chun Liou, Yen-Chi Chang, Yu-Ting Chen, Bo-Yu Wu, Mei-Jie Yang
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Publication number: 20230129196Abstract: A method for manufacturing a semiconductor device, including the following steps. A plurality of first vias are formed in a first dielectric layer in a memory cell region and a peripheral region. A surface treatment is performed on the plurality of first vias to form a plurality of sacrificial layers. The plurality of sacrificial layers are removed to form a plurality of recesses. A plurality of protective layers are formed in the plurality of recesses. A memory device is formed on the first dielectric layer in the memory cell region. A second dielectric layer is formed on the memory device and on the first dielectric layer. A plurality of second vias is formed in the second dielectric layer in the memory cell region and the peripheral region to electrically connect the memory device in the memory cell region and the first vias in the peripheral region, respectively.Type: ApplicationFiled: December 22, 2022Publication date: April 27, 2023Applicant: Winbond Electronics Corp.Inventors: Chi-Ching Liu, Yu-Ting Chen, Chang-Tsung Pai, Shun-Li Lan, Yen-De Lee, Chih-Jung Ni
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Patent number: 11620500Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.Type: GrantFiled: January 11, 2018Date of Patent: April 4, 2023Assignee: WINBOND ELECTRONICS CORP.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Chih-Cheng Fu, Ming-Che Lin, Yu-Ting Chen, Seow-Fong (Dennis) Lim
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Publication number: 20230017479Abstract: A display panel is provided. The display panel includes a sensing region. The display panel includes a capping substrate, a light shielding layer, and a transparent material. The light shielding layer is disposed under the capping substrate. The light shielding layer includes a plurality of holes. The transparent material is disposed under the light shielding layer. The plurality of holes and the transparent material correspond to the sensing region.Type: ApplicationFiled: June 14, 2022Publication date: January 19, 2023Inventors: Yun-Chun LIOU, Yen-Chi CHANG, Yu-Ting CHEN, Bo-Yu WU, Mei-Jie YANG
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Publication number: 20230007928Abstract: A manufacturing method of a transformer includes: winding a first winding wire around a bobbin, wherein two ends of the first winding wire are connected to a first and a second pin of the bobbin respectively; winding a second winding wire around the bobbin, wherein two ends of the second winding wire are connected to a third and a fourth pin of the bobbin respectively; and winding a third and a fourth winding wire in parallel around the bobbin, wherein two ends of the third winding wire are connected to the second and a fifth pin of the bobbin respectively, and two ends of the fourth winding wire are connected to the fifth and a sixth pin respectively. The first, the third and the fourth winding wires form a primary coil, and the second winding wire is a secondary coil.Type: ApplicationFiled: November 29, 2021Publication date: January 12, 2023Inventors: PAO WEI LIN, WEI LIANG LIN, PEI WANG, JIA YAO LIN, YU TING CHEN, CHIEN-CHIH LAI
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Patent number: 11538525Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.Type: GrantFiled: October 6, 2021Date of Patent: December 27, 2022Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Patent number: 11316106Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.Type: GrantFiled: December 2, 2020Date of Patent: April 26, 2022Assignee: Winbond Electronics Corp.Inventors: Chung-Hsuan Wang, Yu-Ting Chen, Tz-Hau Guo, Chang-Hsuan Wu, Chiung-Lin Hsu
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Publication number: 20220068382Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: August 27, 2021Publication date: March 3, 2022Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Publication number: 20220028454Abstract: Provided is a resetting method of a resistive random access memory (RRAM) including the following steps. A first resetting operation and a first verifying operation on the at least one resistive memory cell are performed. Whether to perform a second resetting operation according to a verifying result of the first verifying operation is determined. A second verifying operation is performed after the second resetting operation is determined to be performed and is finished. To determine whether to perform a healing resetting operation according to a verifying result of the second verifying operation, which comprises: performing the healing resetting operation when a verifying current of the second verifying operation is greater than a predetermined current, wherein a resetting voltage of the healing resetting operation is greater than a resetting voltage of the second resetting operation.Type: ApplicationFiled: October 6, 2021Publication date: January 27, 2022Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Ming-Che Lin, Yu-Ting Chen, Chang-Tsung Pai, Shao-Ching Liao, Chi-Ching Liu
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Publication number: 20210366986Abstract: A three-dimensional semiconductor device includes multiple semiconductor device layers on a substrate, wherein each layer includes a first stacked structure, a first gate dielectric layer, a first semiconductor layer, a first channel layer, a first source region, a first drain region, and a first resistive random access memory cell. The first stacked structure on the substrate includes a first insulating layer and a first gate conductor layer. The first gate dielectric layer surrounds a sidewall of the first stacked structure. The first semiconductor layer surrounds a sidewall of the first gate dielectric layer. The first channel layer is in the first semiconductor layer. The first source region and the first drain region are on both sides of the first channel layer in the first semiconductor layer. The first resistive random access memory cell is on a first sidewall of the first semiconductor layer and connected to the first drain region.Type: ApplicationFiled: April 7, 2021Publication date: November 25, 2021Applicant: Winbond Electronics Corp.Inventors: Chang-Tsung Pai, Chiung-Lin Hsu, Yu-Ting Chen, Ming-Che Lin, Chi-Ching Liu