Abstract: A magnetic field structure is provided and includes: two magnetic poles disposed in a magnetic circuit path and opposite to one another to form a space therebetween for receiving an element to be tested; a magnetic field source for providing a magnetic field in the space; and an optical positioning element disposed in one of the two magnetic poles for optically positioning the element to be tested. Therefore, the magnetic field structure can simultaneously provide a strong magnetic field and a precise positioning function.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: A small-area side-capacitor read-only memory device, a memory array and a method for operating the same are provided. The small-area side-capacitor read-only memory device embeds a field-effect transistor in a semiconductor substrate. The field-effect transistor includes a first dielectric layer and a first conductive gate stacked on the first dielectric layer. The side of the first conductive gate extends to the top of the second dielectric layer and connects to the second conductive gate to generate a capacitance effect. The second conductive gate has finger portions connected to a strip portion. Thus, the memory device employs the smallest layout area to generate the highest capacitance value, thereby decreasing the overall area of the read-only memory and performing efficient reading and writing.

Abstract: The present disclosure provides an electromagnetic wave absorbing material, including a core containing iron oxide having a first thermal expansion coefficient; and a shell layer covering the core, which has a second thermal expansion coefficient less than the first thermal expansion coefficient, and the shell layer contains an inorganic compound selected from a group consisting of oxides, nitrides or any combination thereof. The present disclosure further provides a composite structure for suppressing electromagnetic interference including the electromagnetic wave absorbing material as claimed.

Abstract: A high writing rate antifuse array includes at least one sub-memory array including two antifuse memory cells arranged side by side between two neighboring bit lines. Each of two antifuse memory cells includes an antifuse transistor. The antifuse transistor has at least one sharp corner overlapping an antifuse gate above a first gate dielectric layer. Each of two antifuse memory cells includes a selection transistor. The second gate dielectric layers of two selection transistors are connected with each other. Thus, two antifuse memory cells are connected with the same select line and the same word line but are respectively connected with different bit lines. In the present invention, a common source contact is used, and two selection transistors share a channel, whereby to stabilize the source structure, increase the channel width of the selection transistors, and raise the writing rate without increase of overall area of the layout.

Abstract: Devices that convert heat into electricity, and methods for a fabrication of the same are provided. The asymmetric thermo-electrochemical capacitor uses a GO-based positive electrode and a battery-type negative electrode to open up the operating voltage window and enhance the electrical discharge capacity for converting low-grade heat into electricity with excellent efficiency, fast thermo-charging time, and stable cycles. The thermo-electrochemical device includes a carbon-based positive electrode, a conductive polymer or a metal-organic framework as negative electrode, a current collector, and a porous separator.

Abstract: The present disclosure provides a checker and a checking method for a processor circuit. The checking method includes: determining whether a data cache send a data refill request under a branch prediction executing status for obtaining a first result; determining whether data requested by the data refill request is written into a register and calculated under the branch prediction executing status for obtaining a second result; and determining whether the processor circuit has a vulnerability according to the first result and the second result.

Abstract: A nano-twinned crystal film and a method thereof are disclosed. The method of fabricating a nano-twinned crystal film includes utilizing an electrolyte solution including copper salt, acid, and a water or alcohol-soluble organic additive, and performing electrodeposition, under conditions of a current density of 20˜100 mA/cm2, a voltage of 0.2˜1.0V, and a cathode-anode distance of 10˜300 mm, to form the nano-twinned crystal film on a surface at the cathode. The nano-twinned crystal film formed by the method includes a plurality of nano-twinned copper grains and a region of random crystal phases between some of adjacent nano-twinned copper grains, wherein at least some of the nano-twinned copper grains have a pillar cap configuration with a wide top and a narrow bottom.

Abstract: A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Abstract: A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

Abstract: A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.

Abstract: A magnetic field structure is provided and includes: two magnetic poles disposed in a magnetic circuit path and opposite to one another to form a space therebetween for receiving an element to be tested; a magnetic field source for providing a magnetic field in the space; and an optical positioning element disposed in one of the two magnetic poles for optically positioning the element to be tested. Therefore, the magnetic field structure can simultaneously provide a strong magnetic field and a precise positioning function.

Abstract: A low-cost and low-voltage anti-fuse array includes a plurality of sub-memory arrays. In each sub-memory array, the anti-fuse transistor of all anti-fuse memory cells includes an anti-fuse gate commonly used by other anti-fuse transistors. These anti-fuse memory cells are arranged side by side between two adjacent bit-lines, wherein the anti-fuse memory cells in the same row are connected to different bit-lines, and all anti-fuse memory cells are connected to the same selection-line and different word-lines. The present invention utilizes the configuration of common source contacts to achieve a stable source structure and reduce the overall layout area, and meanwhile minimizes the types of control voltage to reduce leakage current.

Abstract: An electrolyte and a fabricating method thereof, and a lithium battery are described. The fabricating method of the electrolyte has steps of: adding a PVDF-based polymer and a PMA-based polymer to a liquid electrolyte to form a mixture, wherein the liquid electrolyte comprises a lithium salt; heating the mixture to between 60 and 100° C. for more than 4 hours, so as to form a transparent solution; and cooling the transparent solution to form the electrolyte. The electrolyte is a gel-state electrolyte between ?60 and 80° C., which is suitable for use as an electrolyte in a lithium battery.

Abstract: A small-area and low-voltage anti-fuse element comprises four first gate dielectric layers each two symmetrically distributed; and an anti-fuse gate formed on the first gate dielectric layers, wherein four corners of the anti-fuse gate respectively overlap corners of the first gate dielectric layers, which are closest to the anti-fuse gate; each of the four corners of the anti-fuse gate is fabricated to have at least one sharp angle. The present invention is characterized in that four first gate dielectric layers share an anti-fuse gate and that the sharp angle has a higher density of charges. Therefore, the present invention can greatly reduce the size of elements, lower the voltage required to puncture the first gate dielectric layer, and decrease the power consumption. The present invention also discloses a small-area and low-voltage anti-fuse array.

Abstract: Devices that convert heat into electricity, and methods for a fabrication of the same are provided. The asymmetric thermo-electrochemical capacitor uses a GO-based positive electrode and a battery-type negative electrode to open up the operating voltage window and enhance the electrical discharge capacity for converting low-grade heat into electricity with excellent efficiency, fast thermo-charging time, and stable cycles. The thermo-electrochemical device includes a carbon-based positive electrode, a conductive polymer or a metal-organic framework as negative electrode, a current collector, and a porous separator.

Abstract: An optical chip package is provided. The optical chip package includes a first transparent substrate, a second transparent substrate, and a spacer layer. The first and second transparent substrates each has a first surface and a second surface opposite the first surface. The first transparent substrate has a thickness that is different than that of the second transparent substrate. The second transparent substrate is disposed over the first transparent substrate, and the spacer layer is bonded between the second surface of the first transparent substrate and the first surface of the second transparent substrate. The recess region extends from the second surface of the second transparent substrate into the first transparent substrate, so that the first transparent substrate has a step-shaped sidewall. A method of forming an optical chip package is also provided.

Abstract: An electronic device which is capable of being bent in a first direction and includes a plurality of light-emitting units and a plurality of conductive patterns overlapping with at least a portion of the plurality of light-emitting units and extending in a second direction. The first direction and the second direction have an angle ? of not greater than 30 degrees.