Abstract: A memory device, includes a memory array for storing a plurality of vector data each of which has an MSB vector and a LSB vector. The memory array includes a plurality of memory units each of which has a first bit and a second bit. The first bit is used to store the MSB vector of each vector data, the second bit is used to store the LSB vector of each vector data. A bit line corresponding to each vector data executes one time of bit-line-setup, and reads the MSB vector and the LSB vector of each vector data according to the bit line. The threshold voltage distribution of each memory unit is divided into N states, where N is a positive integer and N is less than 2 to the power of 2, and the effective bit number stored by each memory unit is less than 2.

Abstract: One aspect of this description relates to a testing apparatus including an advance process control monitor (APCM) in a first wafer, a plurality of pads disposed over and coupled to the APCM. The plurality of pads are in a second wafer. The testing apparatus includes a testing unit disposed between the first wafer and the second wafer. The testing unit is coupled to the APCM. The testing unit includes a metal structure within a dielectric. The testing apparatus includes a plurality of through silicon vias (TSVs) extending in a first direction from the first wafer, through the dielectric of the testing unit, to the second wafer.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: The present disclosure provides a semiconductor wafer. The semiconductor wafer includes: a scribe line between a first row of dies and a second row of dies; and a benchmark circuit disposed adjacent to the scribe line and electrically coupled to a first conductive contact and a second conductive contact. The benchmark circuit includes a first device-under-test (DUT); a second DUT; a first switching circuit configured to selectively couple the first DUT and the second DUT to the first conductive contact; and a second switching circuit configured to selectively couple the first DUT and the second DUT to the second conductive contact.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: A test method includes: generating an error correction code according to a base data; dividing the base data into a plurality of base data sections; generating a plurality of candidate testing data according to the base data, wherein each of the candidate testing data has a plurality of testing data sections, and each of the testing data sections corresponds to each of the base data sections; and, performing a plurality of testing schemes. Each of the testing schemes includes: generating a plurality of write-in test data according to the plurality of candidate testing data, and writing the plurality of write-in test data with the error correction code into a tested device continuously; reading a plurality of mode register values of the tested device and a plurality of readout data from the tested device; and generating a test result according to the plurality of mode register value and the readout data.

Abstract: A surge protection circuit is presented. The surge protection circuit includes an input port for receiving an input voltage; an energy release cell having a first terminal coupled to the input port, a second terminal coupled to ground, and a control terminal coupled to the input port via a first switch device and to the ground via a second switch device. The surge protection circuit is adapted to close the first switch device to enable a current to flow from the input port to ground through the release cell upon occurrence of a positive voltage surge and to close the second switch device to enable a current to flow from ground to the input port through the release cell upon occurrence of a negative voltage surge.

Abstract: A picture display method includes receiving a game picture of a target game from a target container in a process of running the target game, the target game being a cloud game running on the target container; obtaining a control operation on the target game performed on the terminal device, and locally drawing an operation animation according to the control operation; and superposing the operation animation on the received game picture, and displaying, on a user interface, the game picture on which the operation animation is superposed.

Abstract: A clamping device for clamping silicon wafers of different sizes and cleaning same includes a main body and a plurality of clamping mechanisms. The surface of the main body defines a plurality of receiving grooves. Separate circular and concentric rows of clamping mechanisms are radially disposed around a central axis of the main body. The clamping mechanism includes first and second clamping members each received in one of the receiving grooves and are adjustable in respect of working height above or flush with the carrying surface of the main body. The first clamping member is closer to the center axis with respect to the second clamping member. A cleaning device with the clamping device is also disclosed.

Abstract: Net-based checking of a circuit design includes obtaining a circuit design comprising a plurality of polygons. Further, a shape of a first polygon of the plurality of polygons, and a shape of a second polygon of the plurality of polygons is determined. The shape of the first polygon differs from a shape of the second polygon. Violations within the circuit design are detected based on a comparison of the first polygon with the second polygon.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, and a light-sensing region close to the front surface. The image sensor device includes an insulating layer covering the back surface and extending into the semiconductor substrate. The protection layer has a first refractive index, and the first refractive index is less than a second refractive index of the semiconductor substrate and greater than a third refractive index of the insulating layer, and the protection layer conformally and continuously covers the back surface and extends into the semiconductor substrate. The image sensor device includes a reflective structure surrounded by insulating layer in the semiconductor substrate.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: An LDMOS device comprises a well region, first and second implant regions, a gate electrode, first and second source/drain regions, a first STI region, and a first DTI region. The well region is in a substrate and of a first conductivity type. The first implant region is in the substrate and of a second conductivity type. The second implant region is in the well region and of the first conductivity type. The gate electrode extends from above the well region to above the first implant region. The first and second source/drain regions are respectively in the first and second implant regions. The first STI region laterally extends from the second implant region to directly below the gate electrode. The first DTI region extends downwards from a bottom surface of the first STI region into the well region. The first DTI region vertically overlaps with the gate electrode.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a first side, a second side opposite to the first side, and at least one light-sensing region close to the first side. The image sensor device includes a dielectric feature covering the second side and extending into the semiconductor substrate. The dielectric feature in the semiconductor substrate surrounds the light-sensing region. The image sensor device includes a reflective layer in the dielectric feature in the semiconductor substrate, wherein a top portion of the reflective layer protrudes away from the second side, and a top surface of the reflective layer and a top surface of the insulating layer are substantially coplanar.

Abstract: A physiological monitoring system is provided. The physiological monitoring system includes a feature extraction device, an identifier, a processor, a physiological sensing device, and a vital-sign detector. The feature extraction device extracts biological information of an object to generate an extraction signal. The identifier receives the extraction signal and verifies an identity of the object according to the extraction signal. The processor receives the extraction signal and obtains at least one biological feature of the user according to the extraction signal. The physiological sensing device senses a physiological feature to generate a bio-signal. The vital-sign detector estimates vital-sign data of the object according to the bio-signal and the at least one biological feature.

Abstract: A physiological monitoring system is provided. The physiological monitoring system includes a feature extraction device, an identifier, a processor, a physiological sensing device, and a vital-sign detector. The feature extraction device extracts biological information of an object to generate an extraction signal. The identifier receives the extraction signal and verifies an identity of the object according to the extraction signal. The processor receives the extraction signal and obtains at least one biological feature of the user according to the extraction signal. The physiological sensing device senses a physiological feature to generate a bio-signal. The vital-sign detector estimates vital-sign data of the object according to the bio-signal and the at least one biological feature.

Abstract: A materials rack carrying support plates inside, and able to secure or release the support plates by lifting or dropping a handle at the top, includes a frame, a stop assembly, and an assembly for the handle. The stop assembly includes a stop rod, a first pressing plate on an end of the stop rod, and an elastic member resisting against the top frame and the first pressing plate. The handle assembly includes a rotating shaft, the handle and a second pressing plate being fixed to the rotating shaft. By the handle, the second pressing plate can be moved towards the first pressing plate to press down the first pressing plate or moved away from the first pressing plate to release a downward pressure of the first pressing plate.

Abstract: A vital-sign detection system is provided. The vital-sign detection system includes a vital-sign detection device and a controller. The vital-sign detection device is enabled to detect a vital-sign of a user. The controller determines whether the gets in the bed and controls the vital-sign detection device to switch to a disabled mode from a first enabled mode in response to the user getting in the bed. During a period when the vital-sign detection device is in the disabled mode, the controller determines whether the user falls asleep. In response to the user falling asleep, the controller controls the vital-sign detection device to switch to a second enabled mode from the disabled mode.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.