Abstract: The invention discloses an electronic device. The electronic device comprises a body and a function module. The function module is rotatably disposed in the body, and includes a housing, a function component and a rigid-flex circuit board. The housing includes a shaft portion. The shaft portion is engaged to the body. The function component and the rigid-flex circuit board are disposed in the housing. The rigid-flex circuit board includes a rigid board portion and at least a flexible board portion. The rigid board portion is electrically connected to the function component. The flexible board portion is connected to the rigid board portion. The flexible board portion passes through the shaft portion and extends into the body.

Abstract: A package structure includes an optical die, an optical die, a supporting structure, and a lens structure. The optical die includes a photonic region. The optical die is disposed on and electrically coupled to the optical die. The supporting structure is disposed on the optical die, where the electric die is disposed between the supporting structure and the optical die. The lens structure is disposed on the supporting structure and optically coupled to the photonic region of the optical die, where the supporting structure is disposed between the lens structure and the electric die.

Abstract: A metal-insulator-metal (MIM) structure and methods of forming the same for reducing the accumulation of external stress at the corners of the conductor layers are disclosed herein. An exemplary device includes a substrate that includes an active semiconductor device. A stack of dielectric layers is disposed over the substrate. A lower contact is disposed over the stack of dielectric layers. A passivation layer is disposed over the lower contact. A MIM structure is disposed over the passivation layer, the MIM structure including a first conductor layer, a second conductor layer disposed over the first conductor layer, and a third conductor layer disposed over the second conductor layer. A first insulator layer is disposed between the first conductor layer and the second conductor layer. A second insulator layer is disposed between the second conductor layer and the third conductor layer. One or more corners of the third conductor layer are rounded.

Abstract: Via array configurations for metal-insulator-metal (MIM) capacitor structures are disclosed herein. An exemplary MIM capacitor structure includes a capacitor bottom metal layer, a first dielectric layer over the capacitor bottom metal layer, a capacitor middle metal layer over the first dielectric layer, a second dielectric layer over the capacitor middle metal layer, and a capacitor top metal layer over the second dielectric layer. A metal via array, which has a first metal via and a second metal via, is connected to the capacitor top metal layer and the capacitor bottom metal layer. A portion of the capacitor top metal layer covers an area of the second dielectric layer extending from the first metal via to the second metal via. From a top view, the portion of the capacitor top metal layer surrounds the first metal via and the second metal via.

Abstract: A semiconductor packaging structure includes a first passivation layer, a capacitor structure, and a second passivation layer. The capacitor structure is disposed on the first passivation layer. The second passivation layer is disposed on the capacitor structure opposite to the first passivation layer. The second passivation layer has a compressive stress that is smaller than ?0.3 GPa.

Abstract: The present invention relates to an n-type conductive composition comprising a rigid conjugated polymer having a dihedral angle from 0° to 20° and an n-type polymeric cation. Further, the present invention relates to an n-type conductive ink comprising such a composition.

Abstract: The application discloses a method, for building an oscillator frequency adjustment lookup table in a transceiver, wherein the transceiver generates a clock according to a crystal oscillator external to the transceiver for transceiving data. The transceiver includes adjustable capacitor arrays assembly connected to the crystal oscillator, wherein when an equivalent capacitance of the adjustable capacitor assembly is a reference value, the crystal oscillator has a reference frequency, and when the equivalent capacitance changes relative to the reference value, the crystal oscillator correspondingly has a frequency offset relative to the reference frequency. The method includes: performing an interpolation operation according to a first value, a second value, and a third value of the equivalent capacitance, and the corresponding frequency variations, so as to obtain the frequency variations corresponding to a first sub-value between the first value and the second values.

Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.

Abstract: An example connector assembly includes a cage, a first liquid cooling tray, a second liquid cooling tray, and a pressuring spring. The cage includes a frame and partitioning walls. The frame and the partitioning walls define an insertion space. The first liquid cooling tray is provided to a top of the cage, with a lower surface of the first liquid cooling tray constituting an upper wall surface of the insertion space. The second liquid cooling tray is provided to a bottom of the cage, with an upper surface of the second liquid cooling tray constituting a lower wall surface of the insertion space. The pressuring spring is positioned within the insertion space.

Abstract: In a method of manufacturing a semiconductor device, an opening is formed in a first dielectric layer so that a part of a lower conductive layer is exposed at a bottom of the opening, one or more liner conductive layers are formed over the part of the lower conductive layer, an inner sidewall of the opening and an upper surface of the first dielectric layer, a main conductive layer is formed over the one or more liner conductive layers, a patterned conductive layer is formed by patterning the main conductive layer and the one or more liner conductive layers, and a cover conductive layer is formed over the patterned conductive layer. The main conductive layer which is patterned is wrapped around by the cover conductive layer and one of the one or more liner conductive layers.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to improve feature engineering efficiency. An example method disclosed herein includes retrieving a log file in a first file format, the log file containing feature occurrence data, generating a first unit operation based on the first file format to extract the feature occurrence data from the log file to a string, the first unit operation associated with a first metadata tag, generating second unit operations to identify respective features from the feature occurrence data, the second unit operations associated with respective second metadata tags, and generating a first sequence of the first metadata tag and the second metadata tags to create a first vector output file of the feature occurrence data.

Abstract: A connector assembly is provided and includes a guide shielding cage and a heat sink module. The guide shielding cage has at least one insertion space positioned inside. The heat sink module includes a heat dissipating member, a pressure applying elastic member, a lever member and a supporting elastic member. The heat dissipating member has a thermal coupling portion formed downwardly, the lever member is pivoted to the guide shielding cage, the lever member has a pushed end and a pressure applying end, the supporting elastic member upwardly and elastically supports the heat dissipating member. The heat dissipating member is capable of moving between a releasing position which is higher relative to the insertion space and an acting position which is lower relative to the insertion space and where the thermal coupling portion enters into the insertion space.

Abstract: A device structure according to the present disclosure includes a metal-insulator-metal (MIM) stack. The MIM stack includes at least one lower conductor plate layer, a first insulator layer disposed over the at least one lower conductor plate layer, a first conductor plate layer disposed over the first insulator layer, a second insulator layer disposed over the first conductor plate layer, and a second conductor plate layer disposed over the second insulator layer. The device structure further includes a ground via extending through and electrically coupled to a first ground plate in the first conductor plate layer and a first via extending through and electrically coupled to a high voltage plate in the second conductor plate layer. The first ground plate vertically overlaps the high voltage plate and the second insulator layer is different from the first insulator layer.

Abstract: Methods for forming a back-end-of-line (BEOL) passive device structure are provided. A method according to the present disclosure includes depositing a first conductor layer over a substrate, patterning the first conductor layer to form a patterned first conductor layer, depositing a first insulation layer over the patterned first conductor layer, depositing a second conductor layer over the first insulation layer, patterning the second conductor layer to form a patterned second conductor layer, depositing a second insulation layer over the patterned second conductor layer, depositing a third conductor layer over the second insulation layer, and patterning the third conductor layer to form a patterned third conductor layer. The patterning of the first conductor layer includes removing a right-angle edge of the first conductor layer.

Abstract: A resin comprises at least one compound selected from one of the following formulas

Abstract: A semiconductor structure includes a semiconductor substrate and an interconnect structure on the semiconductor structure. The interconnect structure includes a first layer, a second layer over the first layer, a third layer over the second layer, and a fourth layer over the third layer. A first through via extends through the semiconductor substrate, the first layer, and the second layer. A second through via extends through the third layer and the fourth layer. A bottom surface of the second through via contacts a top surface of the first through via.

Abstract: A thickness detection mechanism arranged in a scanner or printer for measuring the thickness of mediums fed through the scanner or printer, which comprising: a conveyor section; at least a idle roller set arranged above the conveyor section, which includes at least a shaft and an idle roller pivotally arranged on the shaft; at least an elastic portion arranged above the shaft; and at least a pressure sensor secured on the elastic portion; wherein the thickness detection mechanism measures the thickness of the medium by measuring the pressure applied on the pressure sensor by the idle roller set as the idle roller set being pushed upward, and thus avoids the medium too thin or too thick to enter the scanner or the printer.

Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.

Abstract: A structured material is provided that includes a substrate and a porous structured polymer layer disposed thereon. The porous structured polymer layer includes a plurality of voids, and has a high hemispherical reflectance a high a hemispherical thermal emittance. The structured material is thus particularly advantageous for cool-roof coatings, enabling surfaces coated by the material to stay cool, even under strong sunlight. The material can be produced via structuring of polymers in a mixture including a solvent and a non-solvent. Sequential evaporation of the solvent and the non-solvent provide a polymer layer with the plurality of voids.

Abstract: The present disclosure provides a connector assembly comprising a shielding cage and a liquid cooling cabin. The shielding cage has an insertion space and a window in communication with the insertion space. The liquid cooling cabin is configured to allow a cooling liquid to circulate and flow inside, the liquid cooling cabin comprises a shell having an opening, a thermal coupling cover provided at the opening of the shell, and an elastic sealing unit sealing a gap between the thermal coupling cover and the shell, the thermal coupling cover having a thermal coupling plate entering into the insertion space via the window of the shielding cage, the thermal coupling plate being capable of elastically moving in a direction close to the shell and elastically restoring in a direction away from the shell by a function of the elastic sealing unit.