Abstract: The disclosure is applicable for the technical field of semiconductor devices manufacturing, and provides a gallium oxide SBD terminal structure. The gallium oxide SBD terminal structure comprises a cathode metal layer, an N+ high-concentration substrate layer, an N? low-concentration Ga2O3 epitaxial layer and an anode metal layer from bottom to top, wherein the N? low-concentration Ga2O3 epitaxial layer is within a range of certain thickness close to the anode metal layer; and a doping concentration below the anode metal layer is greater than a doping concentration on two sides of the anode metal layer. Namely, only a doping concentration of the part outside the corresponding area of the anode metal layer is changed, so that the breakdown voltage of the gallium oxide SBD terminal structure is improved under the condition of guaranteeing low on resistance.

Abstract: A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer.

Abstract: A data migration method for a storage system after expansion and a storage system are provided. After an ith expansion is performed on the storage system, data migration is performed by using an auxiliary balanced incomplete block design. Because a quantity of tuples including any element in the auxiliary balanced incomplete block design is identical, and each migration unit includes an identical quantity of parity chunks, a data migration amount after the expansion is minimized. In this way, time required for data migration after the expansion is significantly reduced, and a delay in a response to a user request that is caused because a data migration operation needs to be performed after the expansion is also reduced.

Abstract: The disclosure is related to the technical field of semiconductors, and provides a method for manufacturing a tilted mesa and a method for manufacturing a detector. The method for manufacturing a tilted mesa comprises: coating a photoresist layer on a mesa region of a chip; heating the chip on which the photoresist layer is coated from a first preset temperature to a second preset temperature; performing etching processing on the heated chip, so as to manufacture a mesa having a preset tilting angle; and removing the photoresist layer on the mesa region of the chip after the mesa is manufactured.

Abstract: The disclosure provides a silicon carbide detector and a preparation method therefor. The silicon carbide detector comprises: a wafer, the wafer sequentially comprises, from bottom to top, a substrate, a silicon carbide P+ layer, an N-type silicon carbide insertion layer, an N+ type silicon carbide multiplication layer, an N-type silicon carbide absorption layer and a silicon carbide N+ layer; the doping concentration of the N-type silicon carbide insertion layer gradually increases from bottom to top, and the doping concentration of the N-type silicon carbide absorption layer gradually decreases from bottom to top; a mesa is etched on the wafer, and the mesa is etched to an upper surface of the silicon carbide P+ layer; an N-type electrode is arranged on an upper surface of the mesa, and a P-type electrode is arranged on an upper surface of a non-mesa region.

Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends update data chunk obtained from to-be-written data to corresponding storage node. The storage node do not directly update, based on the received update data chunks, data block stored in storage device of the storage node, but store the update data chunk into non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node to backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

Abstract: A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

Abstract: A flash memory controller refreshes memory blocks in a flash memory device by setting different refresh cycles for individual memory blocks in the flash memory device. The flash memory controller records a number of erase operations performed on each memory block of the flash memory device. Upon detecting that a bit error rate of a memory block is greater than a preset threshold, the flash memory controller determines a refresh cycle for the memory block based on recorded number of erase operations performed on the memory block, and then refreshes the memory block according to the refresh cycle.

Abstract: The present disclosure relates to semiconductor devices, and in particular, to an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer.

Abstract: An access request processing method is performed by a computer device that includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.

Abstract: A processing node, a computer system, and a transaction conflict detection method, where the processing node includes a processor and a transactional cache. When obtaining a first operation instruction in a transaction for accessing shared data, the processor accesses the transactional cache for caching shared data of a transaction processed by the processing node. If the transactional cache determines that the first operation instruction fails to hit a cache line in the transactional cache, the transactional cache sends a first destination address in the operation instruction to a transactional cache in another processing node. After receiving status information of a cache line hit by the first destination address from the other processing node, the transactional cache determines, based on the received status information, whether the first operation instruction conflicts with a second operation instruction executed by the other processing node.

Abstract: A method for accessing a flash memory device and a flash memory device. After receiving a write request for an address, a flash memory controller obtains an indicator of the address, where the indicator indicates a last access type of the address, which might be a write operation or a read operation. When determining the indicator indicates a write operation, which means the access type for the address is normally write operation, to save time, the flash memory controller perform a fast-write operation on the address, when the indicator indicates a read operation, which means there might be plenty of read operations on the address, to facilitate future read operation, the controller performs a slow-write operation on the address.

Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends update data chunk obtained from to-be-written data to corresponding storage node. The storage node do not directly update, based on the received update data chunks, data block stored in storage device of the storage node, but store the update data chunk into non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node to backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.

Abstract: A memory extensible chip (200) is provided. The chip (200) includes a substrate (240), and a processor (230), a first memory module set (210), and a second memory module set (220) that are integrated on the substrate (240). The processor (230) communicates with at least one memory module in the first memory module set (210) using a first communications interface (250), and the processor (230) communicates with at least one memory module in the second memory module set (220) using a second communications interface (260). A memory module in the first memory module set (210) communicates with a memory module in the second memory module set (220) using a substrate network, where the substrate network is a communications network located inside the substrate (240). In this way, the processor (230) can access a memory module in the first memory module set (210) by using the second memory module set (220).

Abstract: An access request processing method and apparatus, and a computer device are disclosed. The computer device includes a processor, a dynamic random-access memory (DRAM), and a non-volatile memory (NVM). When receiving a write request, the processor may identify an object cache page according to the write request. The processor obtains the to-be-written data from a buffer according to a buffer pointer in the write request, the to-be-written data including a new data chunk to be written into the object cache page. The processor then inserts a new data node into a log chain of the object cache page, where the NVM stores data representing the log chain of the object cache page. The new data node includes information regarding the new data chunk of the object cache page. The computer device provided in this application can reduce system overheads while protecting data consistency.

Abstract: A file data access method and a computer system, where the method includes accessing a page global directory (PGD) of the process using PGD space when accessing first file data by a process, determining, based on access to the PGD and according to a first virtual address of the first file data in file system space, a first PGD entry in the PGD, linking a file page table of the process to the first PGD entry, where the file page table points to a physical address of the file data such that a processor retrieves a first physical address of the first file data in a memory according to the first virtual address using the PGD and the file page table, and accessing the first file data according to the first physical address.

Abstract: An enhanced HFET, comprising a HFET device body.