Patents by Inventor Yu-Cheng Chen
Yu-Cheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240194338Abstract: An auxiliary assessment method for cardiac function performed by a computing unit includes collecting a number of heartbeats and an amount of movement of a subject in a period of time; and calculating a distance per beat to assess cardiac function of the subject. The distance per beat is defined by dividing the amount of movement by the number of heartbeats. A length of the period of time is defined between at least two adjacent heartbeats. The amount of movement corresponds to a cumulative amount of movement in the period of time.Type: ApplicationFiled: July 25, 2023Publication date: June 13, 2024Inventors: Chao-Wen CHEN, Hao-Yun KAO, Yu-Cheng CHUANG, Jo-Nan WU, Wen-Yen CHANG
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Publication number: 20240192744Abstract: In an embodiment, a circuit includes: an error amplifier; a temperature sensor, wherein the temperature sensor is coupled to the error amplifier; a discrete time controller coupled to the error amplifier, wherein the discrete time controller comprises digital circuitry; a multiple bits quantizer coupled to the discrete time controller, wherein the multiple bits quantizer produces a digital code output; and a heating array coupled to the multiple bits quantizer, wherein the heating array is configured to generate heat based on the digital code output.Type: ApplicationFiled: February 20, 2024Publication date: June 13, 2024Inventors: Jui-Cheng HUANG, Yi-Hsing HSIAO, Yu-Jie HUANG, Tsung-Tsun CHEN, Allen Timothy CHANG
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Patent number: 12008239Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.Type: GrantFiled: January 9, 2023Date of Patent: June 11, 2024Assignee: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
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Publication number: 20240188251Abstract: A monitoring and alerting method for a liquid-cooling system includes monitoring a thermal resistance variation of a cold plate of the liquid-cooling system and sending an alert related to the thermal resistance variation. Furthermore, a liquid-cooling system and an electronic device including the same are provided. The liquid-cooling system includes a liquid-cooling module including a cold plate; and a monitoring and alerting module including a control unit, an inlet thermometer in communication with the control unit for measuring a temperature of a liquid inlet of the cold plate, and a heat source thermometer in communication with the control unit for measuring a temperature of a heat source in thermal contact with the cold plate. The control unit produces an alert according to a thermal resistance variation calculated by the inlet thermometer, the heat source thermometer, and a power of the heat source.Type: ApplicationFiled: May 2, 2023Publication date: June 6, 2024Inventors: CHIH CHENG LEE, Tzu-Wei Gu, Chun-Chieh Huang, Yu-Lin Chen
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Publication number: 20240184449Abstract: A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The method includes: sending an erase command sequence configured to erase a first physical erasing unit in a rewritable non-volatile memory module; and sending a write command sequence configured to perform a dummy write operation on a second physical erasing unit in the rewritable non-volatile memory module with correspondence to the erasing of the first physical erasing unit. The dummy write operation is configured to store dummy data to the second physical erasing unit.Type: ApplicationFiled: January 9, 2023Publication date: June 6, 2024Applicant: PHISON ELECTRONICS CORP.Inventors: Wei-Cheng Li, Ping-Cheng Chen, Yu-Chung Shen, Jia-Li Xu
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Patent number: 12000782Abstract: A laser whose emission is modulated by ultrasound is presented. The laser is usually micron-sized. In response to ultrasound modulation, the laser emission increases and decreases. Such a change in emission can be detected by external optical detectors. This type of laser can be used as a new type of imaging modality, in which laser emission in combination with sound waves or ultrasound waves, is used for imaging Laser emission has a much narrower spectral linewidth and stronger intensity than fluorescence and therefore is able to achieve higher sensitivity, whereas sound waves are used to provide a better spatial resolution of the laser emission from the laser. In ultrasound modulated laser based imaging, multiple lasers can be placed inside cells or tissues.Type: GrantFiled: January 9, 2020Date of Patent: June 4, 2024Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGANInventors: Xudong Fan, Xueding Wang, Xuzhou Li, Yu Qin, Xiaotian Tan, Yu-Cheng Chen, Qiushu Chen
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Patent number: 11993779Abstract: Stevia varieties with high a content of RebD, a high content of RebM, and a high content of RebD and RebM containing various SNP markers and UGT isoforms, are disclosed. Methods of screening for the SNPs are also disclosed as well as for using the SNPs in marker assisted breeding. Further provided are methods for introgressing the disclosed SNPs associated with high RebD and high RebM into Stevia plants by selecting plants comprising for one or more SNPs and breeding with such plants to confer such desirable agronomic phenotypes to plant progeny.Type: GrantFiled: March 18, 2021Date of Patent: May 28, 2024Assignee: PureCircle SDN BHDInventors: Avetik Markosyan, Seong Siang Ong, Yeen Yee Wong, Yu Cheng Bu, Jian Ning Chen
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Publication number: 20240170225Abstract: This invention describes a packaging structure for roll-type (wound-type) aluminum conductive polymer capacitor element. Two protective substrates are applied to sandwich a roll-type capacitor element in between with an insulating material surrounding the capacitor element also in between the protective substrates. The protective substrates comprise electrically separated anodic conductive pad and cathodic conductive pad on their surfaces and through holes that pass through the conductive pads. The capacitor element is oriented with its axis perpendicular to the two substrates. The anodic and cathodic leads of the capacitor element pass through the through holes. An anodic external terminal is plated over the anodic conductive pad and a cathodic external terminal is plated over the cathodic conductive pad so that the anodic external terminal is electrically connected to the anodic lead and the cathodic external terminal is electrically connected to the cathodic lead.Type: ApplicationFiled: November 22, 2022Publication date: May 23, 2024Inventors: Yu-Peng Chung, Chia-Wei Li, Wen Cheng Hsu, En-Ming Chen, Che-Chih Tsao
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Patent number: 11989046Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.Type: GrantFiled: February 6, 2023Date of Patent: May 21, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Haruki Mori, Hidehiro Fujiwara, Zhi-Hao Chang, Yangsyu Lin, Yu-Hao Hsu, Yen-Huei Chen, Hung-Jen Liao, Chiting Cheng
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Patent number: 11985324Abstract: Exemplary video processing methods and apparatuses for encoding or decoding a current block by inter prediction are disclosed. Input data of a current block is received and partitioned into sub-partitions and motion refinement is independently performed on each sub-partition. A reference block for each sub-partition is obtained from one or more reference pictures according to an initial motion vector (MV). A refined MV for each sub-partition is derived by searching around the initial MV with N-pixel refinement. One or more boundary pixels of the reference block for a sub-partition is padded for motion compensation of the sub-partition. A final predictor for the current block is generated by performing motion compensation for each sub-partition according to its refined MV. The current block is then encoded or decoded according to the final predictor.Type: GrantFiled: March 13, 2020Date of Patent: May 14, 2024Assignee: HFI INNOVATION INC.Inventors: Yu-Cheng Lin, Chun-Chia Chen, Chih-Wei Hsu, Ching-Yeh Chen, Tzu-Der Chuang, Yu-Wen Huang
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Publication number: 20240150906Abstract: An electrolytic cell includes a cation exchange membrane, a cathode compartment, and an anode compartment. The cathode compartment includes a gas diffusion electrode and a flow channel element, in which the flow channel element is between the cation exchange membrane and the gas diffusion electrode, and has a plurality of flow channels arranged in parallel with each other. The anode compartment includes an anode mesh, in which the cation exchange membrane is between the anode mesh and the flow channel element. A distance between the anode mesh and the gas diffusion electrode is substantially equal to the sum of a first thickness of the cation exchange membrane and a second thickness of the flow channel element. The novel electrolytic cell can combine with a chloralkali electrolytic cell to deal with gaseous CO2 and produce products, e.g., synthesis gas, for other purposes.Type: ApplicationFiled: May 9, 2023Publication date: May 9, 2024Inventors: Hao-Ming CHEN, Tai-Lung CHEN, Wan-Tun HUNG, Yu-Cheng CHEN, Kuo-Ming HUANG, Fu-Da YEN, Che-Jui LIAO
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Publication number: 20240145436Abstract: Composite dielectric structures for semiconductor die assemblies, and associated systems and methods are disclosed. In some embodiments, the composite dielectric structure includes a flexible dielectric layer configured to conform to irregularities (e.g., particles, defects) at a bonding interface of directly bonded semiconductor dies (or wafers). The flexible dielectric layer may include a polymer material configured to deform in response to localized pressure generated by the irregularities during bonding process steps. The composite dielectric structure includes additional dielectric layers sandwiching the flexible dielectric layer such that the composite dielectric structure can provide robust bonding strength to other dielectric layers through the additional dielectric layers. In some embodiments, a chemical vapor deposition process may be used to form the composite dielectric structure utilizing siloxane derivatives as a precursor.Type: ApplicationFiled: December 29, 2023Publication date: May 2, 2024Inventors: Hung Cheng Chen, Yu Chun Chen, Hsuan Chao Hou
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Publication number: 20240133467Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.Type: ApplicationFiled: January 4, 2023Publication date: April 25, 2024Applicant: SUNREX TECHNOLOGY CORP.Inventors: Yu-Xiang GENG, Chun-Chieh CHEN, Ling-Cheng TSENG, Yi-Wen TSAI, Ching-Yao HUANG
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Publication number: 20240136346Abstract: A semiconductor die package includes an inductor-capacitor (LC) semiconductor die that is directly bonded with a logic semiconductor die. The LC semiconductor die includes inductors and capacitors that are integrated into a single die. The inductors and capacitors of the LC semiconductor die may be electrically connected with transistors and other logic components on the logic semiconductor die to form a voltage regulator circuit of the semiconductor die package. The integration of passive components (e.g., the inductors and capacitors) of the voltage regulator circuit into a single semiconductor die reduces signal propagation distances in the voltage regulator circuit, which may increase the operating efficiency of the voltage regulator circuit, may reduce the formfactor for the semiconductor die package, may reduce parasitic capacitance and/or may reduce parasitic inductance in the voltage regulator circuit (thereby improving the performance of the voltage regulator circuit), among other examples.Type: ApplicationFiled: April 17, 2023Publication date: April 25, 2024Inventors: Chien Hung LIU, Yu-Sheng CHEN, Yi Ching ONG, Hsien Jung CHEN, Kuen-Yi CHEN, Kuo-Ching HUANG, Harry-HakLay CHUANG, Wei-Cheng WU, Yu-Jen WANG
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Publication number: 20240135990Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.Type: ApplicationFiled: December 28, 2023Publication date: April 25, 2024Applicant: Winbond Electronics Corp.Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
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Publication number: 20240128375Abstract: A method includes forming first and second semiconductor fins and a gate structure over a substrate; forming a first and second source/drain epitaxy structures over the first and second semiconductor fins; forming an interlayer dielectric (ILD) layer over the first and second source/drain epitaxy structures; etching the gate structure and the ILD layer to form a trench; performing a first surface treatment to modify surfaces of a top portion and a bottom portion of the trench to NH-terminated; performing a second surface treatment to modify the surfaces of the top portion of the trench to N-terminated, while leaving the surfaces of the bottom portion of the trench being NH-terminated; and depositing a first dielectric layer in the trench, wherein the first dielectric layer has a higher deposition rate on the surfaces of the bottom portion of the trench than on the surfaces of the bottom portion of the trench.Type: ApplicationFiled: March 16, 2023Publication date: April 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Yi CHANG, Yu Ying CHEN, Zhen-Cheng WU, Chi On CHUI
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Publication number: 20240126023Abstract: An optical fiber connector includes a connecting unit, an adapter unit, and an attenuation unit. The adapter unit includes an insertion seat connected removably to a main housing of the connecting unit, and two guide frame bodies located respectively at two opposite sides of the insertion seat in a transverse direction. The insertion seat has two insertion holes spaced apart in the transverse direction and extending in a front-rear direction. Each guide frame body extends in the front-rear direction away from the connecting unit. The attenuation unit includes two attenuation components, two rear ferrules, and two front ferrules. The attenuation components are arranged in the transverse direction and disposed within the main housing. The rear ferrules respectively extend rearwardly from rear ends of the attenuation components into the insertion holes. The front ferrules respectively extend forwardly from front ends of the attenuation components through and outwardly of the main housing.Type: ApplicationFiled: January 19, 2023Publication date: April 18, 2024Inventors: Hsien-Hsin HSU, Yu Cheng CHEN, Ke Xue NING, Shu Bin LI
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Package structure comprising buffer layer for reducing thermal stress and method of forming the same
Patent number: 11961777Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.Type: GrantFiled: June 27, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao -
Publication number: 20240118352Abstract: A method for determining a road type includes measuring, for a preset period, a magnetic field of an environment in which an electronic device is located to obtain a plurality of magnetic field values, calculating an absolute value of a difference between every two adjacent magnetic field values among the magnetic field values sorted in chronological order, calculating an average of the absolute values related to the magnetic field values to serve as a variation value for the environment, determining whether the variation value is smaller than a predetermined threshold value, determining that the environment is a surface road when the determination result is affirmative, and determining that the environment is a non-surface road when the determination result is negative.Type: ApplicationFiled: November 23, 2022Publication date: April 11, 2024Inventors: Chia-Cheng WANG, Jyh-Cheng CHEN, Yu-Xin XIAO
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Patent number: D1023802Type: GrantFiled: September 3, 2021Date of Patent: April 23, 2024Assignee: TRON FUTURE TECH INC.Inventors: Yu-Jiu Wang, Chia-Cheng Kung, Yu-Ju Chen, Boon How Teoh