Patents by Inventor Yuichi Okuda

Yuichi Okuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160173115
    Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
    Type: Application
    Filed: February 23, 2016
    Publication date: June 16, 2016
    Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
  • Publication number: 20160164461
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9362932
    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
  • Patent number: 9362931
    Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 7, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takaya Yamamoto, Hideo Nakane, Keisuke Kimura, Yuichi Okuda, Takashi Oshima
  • Patent number: 9300248
    Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: March 29, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Osamu Ozawa, Masashi Horiguchi, Yuichi Okuda, Akihito Anzai
  • Patent number: 9294115
    Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: March 22, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura, Takashi Oshima, Tatsuji Matsuura
  • Publication number: 20160043729
    Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
    Type: Application
    Filed: October 23, 2015
    Publication date: February 11, 2016
    Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
  • Publication number: 20160043712
    Abstract: Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.
    Type: Application
    Filed: October 22, 2015
    Publication date: February 11, 2016
    Inventor: Yuichi OKUDA
  • Patent number: 9258006
    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 9, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
  • Patent number: 9258003
    Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: February 9, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura
  • Publication number: 20150381192
    Abstract: There is provided a semiconductor device using low electric power and a small area which can realize highly accurate calibration. The semiconductor device according to the embodiment includes an A/D conversion unit, and a hold signal generating circuit which is coupled to an input side of the A/D conversion unit, and has a hold period not less than two cycles of the A/D conversion unit. The hold signal generating circuit includes: an SC integrator including an input buffer coupled to the input side of the A/D conversion unit, and feedback capacitor coupled to an input and an output of the input buffer; and a logic circuit which compares an output signal of plural bits outputted from the A/D conversion unit with a first and a second threshold values, and outputs a control signal which controls polarity of the SC integrator according to a comparison result.
    Type: Application
    Filed: June 25, 2015
    Publication date: December 31, 2015
    Inventors: Takaya YAMAMOTO, Hideo NAKANE, Keisuke KIMURA, Yuichi OKUDA, Takashi OSHIMA
  • Publication number: 20150341043
    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
    Type: Application
    Filed: August 4, 2015
    Publication date: November 26, 2015
    Inventors: Keisuke KIMURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO
  • Patent number: 9184755
    Abstract: A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: November 10, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
  • Patent number: 9177182
    Abstract: Provided is a semiconductor device for wireless communication which achieves a reduction in leakage power and allows an improvement in power efficiency. For example, to external terminals, an antenna driver section for driving an antenna and a rectifying section for rectifying input power from the antenna are coupled. The antenna driver section includes pull-up PMOS transistors and pull-down NMOS transistors. In the rectifying section, a power supply voltage generated by a full-wave rectifying circuit is boosted by a voltage boosting circuit. For example, when a supply of a power supply voltage from a battery is stopped, a power supply voltage resulting from the boosting by the voltage boosting circuit is supplied to the bulk of each of the pull-up PMOS transistors.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 3, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Yuichi Okuda
  • Publication number: 20150293552
    Abstract: A current generation circuit including a first and a second bipolar transistors, a current distribution circuit that makes a first current and a second current flow through the first and second bipolar transistors, respectively, the first current and the second current corresponding to a first control voltage, a first NMOS transistor disposed between the first bipolar transistor and the first current distribution circuit, a second NMOS transistor disposed between the second bipolar transistor and the first current distribution circuit, a first resistive element, a first operational amplifier that outputs the second control voltage to the gates of the first and the second NMOS transistors according to a drain voltage of the first NMOS transistor and a reference bias voltage, and a second operational amplifier that generates the first control voltage according to a drain voltage of the second NMOS transistor and the reference bias voltage.
    Type: Application
    Filed: March 26, 2015
    Publication date: October 15, 2015
    Inventors: Atsushi MOTOZAWA, Yuichi OKUDA
  • Publication number: 20150256193
    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 10, 2015
    Inventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
  • Publication number: 20150249459
    Abstract: To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 3, 2015
    Inventors: Takashi OSHIMA, Tatsuji MATSUURA, Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA
  • Patent number: 9124284
    Abstract: An analog-to-digital converter circuit having a simple design and capable of preventing an increase in surface area and other problems. An analog-to-digital converter circuit for converting an analog input signal to a digital quantity includes an analog-to-digital converter unit that converts analog input signals to pre-correction digital values, and a corrector unit that digitally corrects the pre-connection digital values output from the analog-to-digital converter unit. The corrector unit includes a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying the weighting coefficients provided for each bit by each bit of the pre-correction digital value output from the A/D converter unit and summing them, and a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based on the post-correction digital value and an approximate value for the post-correction digital value.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: September 1, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Keisuke Kimura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto
  • Publication number: 20150229322
    Abstract: A differential signal is amplified by passive amplification which does not a reference of a common-mode voltage. At this time, the voltage of the differential signal is passive-amplified twice before carrying out a successive approximation type analog-digital conversion operation. The passive amplification is attained by providing a plurality of capacitances which carry out a sampling operation, and switching these connection relation by using switches. Without being accompanied by the increase of the consumed power and the chip size, an influence by the noise of s comparator is reduced to a half so that the effective resolution can be increased for one bit.
    Type: Application
    Filed: April 21, 2015
    Publication date: August 13, 2015
    Inventors: Yuichi OKUDA, Hideo NAKANE, Takaya YAMAMOTO, Keisuke KIMURA, Takashi OSHIMA, Tatsuji MATSUURA
  • Patent number: 9100034
    Abstract: A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: August 4, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takashi Oshima, Tatsuji Matsuura, Yuichi Okuda, Hideo Nakane, Takaya Yamamoto, Keisuke Kimura