Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

Abstract: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

Abstract: A semiconductor integrated circuit is provided with an external interface circuit, which includes a clock generation circuit for generating a synchronous clock signal to establish synchronization between data input and output through input and output of a data string sectioned at fixed intervals. The clock generation circuit includes a self-excited oscillator circuit serving as an oscillation source for the synchronous clock signal, and a control circuit for trimming the oscillation frequency of the self-excited oscillator circuit. The control circuit detects the sections made at the fixed intervals to the data string, measures the section interval based on an oscillation output of the self-excited oscillator circuit, and controls the oscillation frequency of the self-excited oscillator circuit to match the measurement value to a target value.

Abstract: A semiconductor integrated circuit is provided with an external interface circuit, which includes a clock generation circuit for generating a synchronous clock signal to establish synchronization between data input and output through input and output of a data string sectioned at fixed intervals. The clock generation circuit includes a self-excited oscillator circuit serving as an oscillation source for the synchronous clock signal, and a control circuit for trimming the oscillation frequency of the self-excited oscillator circuit. The control circuit detects the sections made at the fixed intervals to the data string, measures the section interval based on an oscillation output of the self-excited oscillator circuit, and controls the oscillation frequency of the self-excited oscillator circuit to match the measurement value to a target value.

Abstract: There is provided a semiconductor integrated circuit that hardly causes an unnecessary operation time for variable control over an operating frequency and an internal power supply voltage. A CPU specifies an operational clock signal frequency to a clock generation circuit and an internal power supply voltage to a power supply circuit. The power supply circuit comprises a voltage regulator and a determination circuit to determine a transition state to a specified internal power supply voltage. The CPU uses a first signal to notify which time point the power supply voltage variable control start to the power supply circuit. The power supply circuit returns a second signal to the CPU to notify at which time point the power supply voltage variable control terminated.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: The data for being processed are transmitted by utilizing a daisy chain constitution using a plurality of semiconductor integrated circuit devices each having an input terminal for receiving an input signal containing any one of an instruction, a data, a position where the data exists or a timing signal, and an output terminal for producing a signal formed in an internal circuit in response to the input signal or fed through the input terminal, wherein among the plurality of semiconductor integrated circuit devices, the output terminal of the semiconductor integrated circuit device in the preceding stage and the corresponding input terminal of the semiconductor integrated circuit device of the next stage are connected together.

Abstract: A semiconductor integrated circuit is provided with an external interface circuit, which includes a clock generation circuit for generating a synchronous clock signal to establish synchronization between data input and output through input and output of a data string sectioned at fixed intervals. The clock generation circuit includes a self-excited oscillator circuit serving as an oscillation source for the synchronous clock signal, and a control circuit for trimming the oscillation frequency of the self-excited oscillator circuit. The control circuit detects the sections made at the fixed intervals to the data string, measures the section interval based on an oscillation output of the self-excited oscillator circuit, and controls the oscillation frequency of the self-excited oscillator circuit to match the measurement value to a target value.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and so controlling the delay time of the variable delay circuit that they are brought into agreement with each other, wherein the clock-generating circuit and an internal circuit to be operated by the clock signals formed thereby are formed on a common semiconductor substrate, and an element-forming region in which the clock-generating circuit is formed is electrically isolated from an element-forming region in which the digital circuit is constituted on the semiconductor substrate relying upon the element-isolation technology. The power-source passages, too, are formed independently of other digital circuits.

Abstract: There are provided a semiconductor memory device incorporating an ECC which enables an efficient test with high accuracy by a simplified structure and can shorten the test time and a test method thereof. A semiconductor memory device has an ECC circuit capable of correcting, from an m-bit information code and an n-bit check code stored in an information storing part, an error of the information code to x bits, and a parallel test circuit for receiving an information code and a check code for test with the same bits stored in the information storing part and deciding a defect with the x+1 bits or more as being defective. The parallel test circuit decides a defect with the x+1 bits or more for one piece of position information as a defective chip.

Abstract: A semiconductor integrated circuit capable of protection from card hacking, by which erroneous actions are actively induced by irradiation with light and protected secret information is illegitimately acquired, is to be provided. Photodetectors, configured by a standard logic process, hardly distinguishable from other circuits and consumes very little standby power, are mounted on a semiconductor integrated circuit, such as an IC card microcomputer. Each of the photodetectors, for instance, has a configuration in which a first state is held in a static latch by its initializing action and reversal to a second state takes place when semiconductor elements in a state of non-conduction, constituting the static latch of the first state, is irradiated with light. A plurality of photodetectors are arranged in a memory cell array. By incorporating the static latch type photodetector into the memory array, they can be arranged inconspicuously.

Abstract: A clock generation circuit including a clock duty adjusting circuit in the subsequent stage of a variable delay circuit to control the delay of the variable delay circuit with the rising edge of an external clock. When the phase of the rising edge is matched with the reference clock, the duty of an output clock is matched with the duty of the reference clock by adjusting the pulse width of the signal with the duty adjusting circuit at the falling edge.

Abstract: A DLL circuit or the like is configured so as to be capable of measuring the optimum number of cycles for a delay amount from the input of an external clock to the output of data through the use of a variable delay circuit and performing lock according to the measured number of cycles, whereby a clock generation circuit having a wide lock range can be implemented regardless of the performance of the variable delay circuit and a clock access time.