Patents by Inventor Yuji Awano
Yuji Awano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080169563Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.Type: ApplicationFiled: September 14, 2007Publication date: July 17, 2008Applicant: FUJITSU LIMITEDInventors: Yuji Awano, Masataka Mizukoshi
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Publication number: 20080111164Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.Type: ApplicationFiled: December 21, 2007Publication date: May 15, 2008Applicant: FUJITSU LIMITEDInventor: Yuji AWANO
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Patent number: 7332810Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.Type: GrantFiled: June 8, 2006Date of Patent: February 19, 2008Assignee: Fujitsu LimitedInventor: Yuji Awano
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Patent number: 7311889Abstract: The invention provides a process for production of carbon nanotubes whereby a laminate prepared by alternating lamination of a metal catalyst and a material other than the metal catalyst is cut to expose the laminated structure, and carbon nanotubes are grown on the metal catalyst at the cut surface of the laminate. The process results in high-quality carbon nanotubes, with minimized bundle growth, which are each individually and independently arranged in a highly precise manner at prescribed locations. The invention also provides a carbon nanotube production process comprising a step of preparing a substrate which is inclined in one or two dimensions from a specific highly symmetrical crystal orientation and vapor depositing a metal catalyst along the atomic steps appearing on the surface of the substrate, and a step of growing the carbon nanotubes by chemical vapor deposition (CVD) using the metal catalyst as nuclei.Type: GrantFiled: June 19, 2003Date of Patent: December 25, 2007Assignee: Fujitsu LimitedInventors: Yuji Awano, Yoshitaka Yamaguchi, Kenji Arinaga, Shozo Fujita
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Publication number: 20070267735Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.Type: ApplicationFiled: February 15, 2007Publication date: November 22, 2007Applicant: FUJITSU LIMITEDInventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
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Publication number: 20070253889Abstract: The invention provides a process for production of carbon nanotubes whereby a laminate prepared by alternating lamination of a metal catalyst and a material other than the metal catalyst is cut to expose the laminated structure, and carbon nanotubes are grown on the metal catalyst at the cut surface of the laminate. The process results in high-quality carbon nanotubes, with minimized bundle growth, which are each individually and independently arranged in a highly precise manner at prescribed locations. The invention also provides a carbon nanotube production process comprising a step of preparing a substrate which is inclined in one or two dimensions from a specific highly symmetrical crystal orientation and vapor depositing a metal catalyst along the atomic steps appearing on the surface of the substrate, and a step of growing the carbon nanotubes by chemical vapor deposition (CVD) using the metal catalyst as nuclei.Type: ApplicationFiled: June 19, 2003Publication date: November 1, 2007Inventors: Yuji Awano, Yoshitaka Yamaguchi, Kenji Arinaga, Shozo Fujita
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Publication number: 20060290003Abstract: A Ti film is pattern-formed on a desired portion on a silicon substrate, and a Co film is formed on the substrate so as to cover the Ti film. CNTs are formed only on a portion, under which the Ti film is formed, of the surface of the Co film at approximately 600° C. by a thermal CVD method. The length of the CNT can be controlled by adjusting the thickness of the Ti film.Type: ApplicationFiled: July 14, 2005Publication date: December 28, 2006Applicant: FUJITSU LIMITEDInventors: Akio Kawabata, Mizuhisa Nihei, Masahiro Horibe, Shintaro Sato, Daiyu Kondo, Yuji Awano
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Publication number: 20060226551Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.Type: ApplicationFiled: June 8, 2006Publication date: October 12, 2006Applicant: FUJITSU LIMITEDInventor: Yuji Awano
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Patent number: 7084507Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.Type: GrantFiled: March 28, 2002Date of Patent: August 1, 2006Assignee: Fujitsu LimitedInventor: Yuji Awano
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Patent number: 6885041Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.Type: GrantFiled: December 2, 2002Date of Patent: April 26, 2005Assignee: Fujitsu LimitedInventor: Yuji Awano
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Publication number: 20050067693Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.Type: ApplicationFiled: March 10, 2004Publication date: March 31, 2005Applicant: FUJITSU LIMITEDInventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
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Patent number: 6800886Abstract: The semiconductor device comprises insulation films 30a-30f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24a, 24b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.Type: GrantFiled: May 12, 2003Date of Patent: October 5, 2004Assignee: Fujitsu LimitedInventor: Yuji Awano
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Publication number: 20030214054Abstract: The electron device of the present invention has a carbon-based linear structural body including at least one conductive particle, a first electrode and a second electrode disposed at both end of the carbon-based liner structural body, so as to subject the carbon-based liner structural body including at least one conductive particle to connect between the first electrode and the second electrode. A process of manufacturing the electron device includes steps of: forming a carbon-based liner structural body including at least one conductive particle, using a catalyst of a first island and a second island selected from two or more of islands of the catalyst on a substrate; and forming a first electrode and a second electrode so as to connect the first electrode with the first island and one end of the carbon-based liner structural body, and the second electrode with the second island and the other end of the carbon-based liner structural body.Type: ApplicationFiled: May 19, 2003Publication date: November 20, 2003Applicants: FUJITSU LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGYInventors: Yuji Awano, Kazuhiko Matsumoto
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Publication number: 20030209802Abstract: The semiconductor device comprises insulation films 30a-30f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24a, 24b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.Type: ApplicationFiled: May 12, 2003Publication date: November 13, 2003Applicant: FUJITSU LIMITEDInventor: Yuji Awano
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Publication number: 20030124717Abstract: A method of manufacturing carbon cylindrical structures, as represented by carbon nanotubes, by growing them on a substrate using a chemical vapor deposition (CVD) method, comprising the steps of implanting metal ions to the substrate surface and then growing the carbon cylindrical structures using the metal ions as a catalyst. A method of manufacturing carbon nanotubes comprising a step of using nano-carbon material as seed material for growing carbon nanotubes is also disclosed. A biopolymer detection device comprising vibration inducing means for inducing vibration, binding means capable of resonating with the vibration induced by the vibration inducing means and capable of binding or interacting with a target biopolymer, and detection means for detecting whether or not the binding means have bound or interacted with the target biopolymer, is also disclosed.Type: ApplicationFiled: November 25, 2002Publication date: July 3, 2003Inventors: Yuji Awano, Akio Kawabata, Shozo Fujita
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Publication number: 20030094637Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.Type: ApplicationFiled: December 2, 2002Publication date: May 22, 2003Applicant: FUJITSU LIMITEDInventor: Yuji Awano
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Patent number: 6509586Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.Type: GrantFiled: February 28, 2001Date of Patent: January 21, 2003Assignee: Fujitsu LimitedInventor: Yuji Awano
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Publication number: 20020163079Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.Type: ApplicationFiled: March 28, 2002Publication date: November 7, 2002Applicant: FUJITSU LIMITEDInventor: Yuji Awano
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Publication number: 20010028067Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.Type: ApplicationFiled: February 28, 2001Publication date: October 11, 2001Applicant: FUJITSU LIMITEDInventor: Yuji Awano
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Patent number: 5698868Abstract: A high-speed heterojunction transistor includes a first region for controlling current, and a second region for receiving carriers which have passed the first region. An energy level difference between a lowermost valley of energy and an upper valley of energy in the conduction band of a semiconductor material constituting the second region is greater than that of a semiconductor material constituting the first region.Type: GrantFiled: February 3, 1995Date of Patent: December 16, 1997Assignee: Fujitsu LimitedInventors: Yuji Awano, Yasutake Hirachi, Kohki Hikosaka