Patents by Inventor Yuji Awano

Yuji Awano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080169563
    Abstract: A semiconductor package is disclosed that includes a semiconductor device; a circuit board; and a connection mechanism including a first conductive terminal provided on the semiconductor device, and a second conductive terminal provided on the circuit board side, the connection mechanism electrically connecting the semiconductor device and the circuit board via the first conductive terminal and the second conductive terminal. At least one of the first conductive terminal and the second conductive terminal of the connection mechanism includes one or more carbon nanotubes each having one end thereof fixed to the surface of the at least one of the first conductive terminal and the second conductive terminal, and extending in a direction away from the surface. The first conductive terminal and the second conductive terminal engage each other through the carbon nanotubes.
    Type: Application
    Filed: September 14, 2007
    Publication date: July 17, 2008
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Awano, Masataka Mizukoshi
  • Publication number: 20080111164
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Application
    Filed: December 21, 2007
    Publication date: May 15, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Yuji AWANO
  • Patent number: 7332810
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: February 19, 2008
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 7311889
    Abstract: The invention provides a process for production of carbon nanotubes whereby a laminate prepared by alternating lamination of a metal catalyst and a material other than the metal catalyst is cut to expose the laminated structure, and carbon nanotubes are grown on the metal catalyst at the cut surface of the laminate. The process results in high-quality carbon nanotubes, with minimized bundle growth, which are each individually and independently arranged in a highly precise manner at prescribed locations. The invention also provides a carbon nanotube production process comprising a step of preparing a substrate which is inclined in one or two dimensions from a specific highly symmetrical crystal orientation and vapor depositing a metal catalyst along the atomic steps appearing on the surface of the substrate, and a step of growing the carbon nanotubes by chemical vapor deposition (CVD) using the metal catalyst as nuclei.
    Type: Grant
    Filed: June 19, 2003
    Date of Patent: December 25, 2007
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Yoshitaka Yamaguchi, Kenji Arinaga, Shozo Fujita
  • Publication number: 20070267735
    Abstract: A plurality of conductive pads (2) are formed on a mounting surface of a mounting board. Conductive pads (11) are formed on a principal surface of a semiconductor chip (10) at positions corresponding to the conductive pads of the mounting board, when the principal surface faces toward the mounting board. A plurality of conductive nanotubes (12) extend from the conductive pads of one of the mounting board and the semiconductor chip. A press mechanism (3) presses the semiconductor chip against the mounting board and restricts a position of the semiconductor chip on the mounting surface to mount the semiconductor chip on the mounting board, in a state that tips of the conductive nanotubes are in contact with the corresponding conductive pads not formed with the conductive nanotubes.
    Type: Application
    Filed: February 15, 2007
    Publication date: November 22, 2007
    Applicant: FUJITSU LIMITED
    Inventors: Yuji Awano, Masataka Mizukoshi, Taisuke Iwai, Tomoji Nakamura
  • Publication number: 20070253889
    Abstract: The invention provides a process for production of carbon nanotubes whereby a laminate prepared by alternating lamination of a metal catalyst and a material other than the metal catalyst is cut to expose the laminated structure, and carbon nanotubes are grown on the metal catalyst at the cut surface of the laminate. The process results in high-quality carbon nanotubes, with minimized bundle growth, which are each individually and independently arranged in a highly precise manner at prescribed locations. The invention also provides a carbon nanotube production process comprising a step of preparing a substrate which is inclined in one or two dimensions from a specific highly symmetrical crystal orientation and vapor depositing a metal catalyst along the atomic steps appearing on the surface of the substrate, and a step of growing the carbon nanotubes by chemical vapor deposition (CVD) using the metal catalyst as nuclei.
    Type: Application
    Filed: June 19, 2003
    Publication date: November 1, 2007
    Inventors: Yuji Awano, Yoshitaka Yamaguchi, Kenji Arinaga, Shozo Fujita
  • Publication number: 20060290003
    Abstract: A Ti film is pattern-formed on a desired portion on a silicon substrate, and a Co film is formed on the substrate so as to cover the Ti film. CNTs are formed only on a portion, under which the Ti film is formed, of the surface of the Co film at approximately 600° C. by a thermal CVD method. The length of the CNT can be controlled by adjusting the thickness of the Ti film.
    Type: Application
    Filed: July 14, 2005
    Publication date: December 28, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Akio Kawabata, Mizuhisa Nihei, Masahiro Horibe, Shintaro Sato, Daiyu Kondo, Yuji Awano
  • Publication number: 20060226551
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Application
    Filed: June 8, 2006
    Publication date: October 12, 2006
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Awano
  • Patent number: 7084507
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: August 1, 2006
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Patent number: 6885041
    Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.
    Type: Grant
    Filed: December 2, 2002
    Date of Patent: April 26, 2005
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Publication number: 20050067693
    Abstract: Disclosed is a semiconductor device including a SiC substrate and a heat conductor formed in a hole in the SiC substrate and made of a linear structure of carbon elements.
    Type: Application
    Filed: March 10, 2004
    Publication date: March 31, 2005
    Applicant: FUJITSU LIMITED
    Inventors: Mizuhisa Nihei, Masahiro Horibe, Yuji Awano, Kazukiyo Joshin
  • Patent number: 6800886
    Abstract: The semiconductor device comprises insulation films 30a-30f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24a, 24b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: October 5, 2004
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Publication number: 20030214054
    Abstract: The electron device of the present invention has a carbon-based linear structural body including at least one conductive particle, a first electrode and a second electrode disposed at both end of the carbon-based liner structural body, so as to subject the carbon-based liner structural body including at least one conductive particle to connect between the first electrode and the second electrode. A process of manufacturing the electron device includes steps of: forming a carbon-based liner structural body including at least one conductive particle, using a catalyst of a first island and a second island selected from two or more of islands of the catalyst on a substrate; and forming a first electrode and a second electrode so as to connect the first electrode with the first island and one end of the carbon-based liner structural body, and the second electrode with the second island and the other end of the carbon-based liner structural body.
    Type: Application
    Filed: May 19, 2003
    Publication date: November 20, 2003
    Applicants: FUJITSU LIMITED, NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yuji Awano, Kazuhiko Matsumoto
  • Publication number: 20030209802
    Abstract: The semiconductor device comprises insulation films 30a-30f formed on a semiconductor substrate 10, and a thermal conductor 42 buried in the insulation films. The thermal conductor is formed on a tube structure of carbon atoms. The thermal conductor is formed on a tube structure of carbon atoms, which is a material of very high thermal conductivity, can effectively radiate heat of a very high generated in semiconductor elements, etc., such as transistors 24a, 24b, etc. Accordingly, the semiconductor device can have good heat radiation characteristics.
    Type: Application
    Filed: May 12, 2003
    Publication date: November 13, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Awano
  • Publication number: 20030124717
    Abstract: A method of manufacturing carbon cylindrical structures, as represented by carbon nanotubes, by growing them on a substrate using a chemical vapor deposition (CVD) method, comprising the steps of implanting metal ions to the substrate surface and then growing the carbon cylindrical structures using the metal ions as a catalyst. A method of manufacturing carbon nanotubes comprising a step of using nano-carbon material as seed material for growing carbon nanotubes is also disclosed. A biopolymer detection device comprising vibration inducing means for inducing vibration, binding means capable of resonating with the vibration induced by the vibration inducing means and capable of binding or interacting with a target biopolymer, and detection means for detecting whether or not the binding means have bound or interacted with the target biopolymer, is also disclosed.
    Type: Application
    Filed: November 25, 2002
    Publication date: July 3, 2003
    Inventors: Yuji Awano, Akio Kawabata, Shozo Fujita
  • Publication number: 20030094637
    Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.
    Type: Application
    Filed: December 2, 2002
    Publication date: May 22, 2003
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Awano
  • Patent number: 6509586
    Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: January 21, 2003
    Assignee: Fujitsu Limited
    Inventor: Yuji Awano
  • Publication number: 20020163079
    Abstract: An integrated circuit device having vias having good resistance to migration causing the breaking of a wiring line, or an integrated circuit device having a wiring structure that is fined by breaking the limit of lithography technique is provided. The former device comprises a plurality of elements fabricated on a semiconductor substrate, wiring lines for making the elements and the integrated circuit device function, and vias for interconnecting wiring lines in separate layers, the via being formed of one or more cylindrical structures made up of carbon atoms. The latter device comprises a plurality of elements fabricated on a semiconductor substrate and wiring members for making the elements and the integrated circuit device function, at least part of the wiring members being formed of one or more cylindrical structures made up of carbon atoms.
    Type: Application
    Filed: March 28, 2002
    Publication date: November 7, 2002
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Awano
  • Publication number: 20010028067
    Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.
    Type: Application
    Filed: February 28, 2001
    Publication date: October 11, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Awano
  • Patent number: 5698868
    Abstract: A high-speed heterojunction transistor includes a first region for controlling current, and a second region for receiving carriers which have passed the first region. An energy level difference between a lowermost valley of energy and an upper valley of energy in the conduction band of a semiconductor material constituting the second region is greater than that of a semiconductor material constituting the first region.
    Type: Grant
    Filed: February 3, 1995
    Date of Patent: December 16, 1997
    Assignee: Fujitsu Limited
    Inventors: Yuji Awano, Yasutake Hirachi, Kohki Hikosaka