Abstract: A heterojunction semiconductor device includes an unipolar transistor having, a collector layer, a base layer, a collector side barrier layer provided between the collector layer and base layer, an emitter layer, and an emitter side barrier layer provided between the base layer and the emitter layer. The emitter side barrier layer has a thickness for tunneling a carrier from the emitter and base layer and injecting the carrier into the base layer according to a predetermined voltage applied between the emitter and base layers, the base layer includes a superlattice structure. The superlattice structure includes a plurality thin barrier layers and a thin well layer for forming a mini-band through which the injected carrier can move and a mini-band gap with which the injected carrier collides.

Abstract: A semiconductor device comprises a channel of a semiconductor material for passing carriers, a carrier injecting part for injecting the carriers into the channel and establishing an ohmic contact with the channel at a first location, a carrier collecting part for collecting the carriers from the channel, the carrier collecting part establishing an ohmic contact with the channel at a second, different location, a carrier control part provided on the channel at a third location located between the first and second locations, the carrier control part being applied with a control voltage and controlling the passage of the carriers through the channel from the carrier injecting means to the carrier collecting means in response to the control voltage, and an acceleration part provided between the first and third locations including the third location.

Abstract: A semiconductor device comprises a substrate having a stepped upper major surface, an emitter layer of a semiconductor material provided on the stepped upper major surface of the substrate and having a corresponding stepped upper major surface, a base layer provided on stepped upper major surface of the emitter layer and comprising a plurality of channels of carriers and a plurality of control regions for controlling the passage of carriers through the control regions, and a collector layer of a semiconductor material provided on the base layer for collecting the carriers that have passed through the channels. Each channel extends from the emitter layer to the collector layer, and at least one channel and one control region are provided adjacent with each other in correspondence to each step of the upper major surface of the emitter layer.

Abstract: A semiconductor device comprises a substrate having a stepped upper major surface, an emitter layer of a semiconductor material provided on the stepped upper major surface of the substrate and having a corresponding stepped upper major surface, a base layer provided on stepped upper major surface of the emitter layer and comprising a plurality of channels of carriers and a plurality of control regions for controlling the passage of carriers through the control regions, and a collector layer of a semiconductor material provided on the base layer for collecting the carriers that have passed through the channels. Each channel extends from the emitter layer to the collector layer, and at least one channel and one control region are provided adjacent with each other in correspondence to each step of the upper major surface of the emitter layer.

Abstract: A semiconductor device having a selectively doped heterostructure comprises a substrate, a channel layer, a carrier supplying layer, and electrodes provided on the carrier supplying layer. The channel layer and the carrier supplying layer form a heterojunction interface at a boundary between the channel layer and the carrier supplying layer with a two-dimensional electron gas formed in the channel layer along the heterojunction interface. The carrier supplying layer and the channel layer have respective compositions determined such that the .GAMMA. valley of the conduction band of the carrier supplying layer has an energetical level higher than a corresponding energetical level of the .GAMMA.

Abstract: A semiconductor device generally has an anode layer, a first semiconductor layer, a first cladding layer having a superlattice structure, an active layer having a superlattice structure, a second cladding layer having a superlattice structure, a cathode barrier layer, a second semiconductor layer, and a cathode layer. The cathode barrier layer allows electrons to tunnel therethrough when a voltage is applied across the anode and cathode layers so that a potential on a side of the superlattices is positive with respect to the cathode barrier layer. The active layer has the superlattice with a bottom energy of a miniband from which electrons transit to a lower miniband with a light emission which bottom energy is smaller than those of the superlattices of the first and second cladding layers.

Abstract: A high-speed compound semiconductor device includes semiconductor layers of a group III-V alloy laminated in a vertical direction. The device uses a base electrode that contacts side walls and covers a step portion of a base layer. The device includes an intermediate layer positioned between and comprising a different semiconductor material than that of base and collector layers. The intermediate layer has a different etching rate than those of the base and collector layers. The intermediate layer can be a collector-side barrier layer formed between the collector and base layers in a HET or RHET device. The device of the present invention has reduced capacitance between the base and collector layers and reduced base layer resistance.

Abstract: A complementary semiconductor device (CMOS gate) including a p-channel transistor (PMOS FET) and an n-channel transistor (NMOS FET). A silicon substrate, a channel layer for the p-channel transistor which comprises a first Si.sub.1-x Ge.sub.x layer, a Ge layer, and a second Si.sub.1-x Ge.sub.x layer are formed in sequence on the silicon substrate. A silicon layer, as another channel layer for the n-channel transistor, is formed on the channel layer. The ratio "x" of the first Si.sub.1-x Ge.sub.x layer is continuously increased from 0 to 1, and the ratio "x" of the second Si.sub.1-x Ge.sub.x layer is continuously decreased from 1 to 0.

Abstract: A high-speed compound semiconductor device includes semiconductor layers of a group III-V alloy laminated in a vertical direction. The device uses a base electrode that contacts side walls and covers a step portion of a base layer. The device includes an intermediate layer positioned between and comprising a different semiconductor material than that of base and collector layers. The intermediate layer has a different etching rate than those of the base and collector layers. The intermediate layer can be a collector-side barrier layer formed between the collector and base layers in a HET or RHET device. The device of the present invention has reduced capacitance between the base and collector layers and reduced base layer resistance.

Abstract: A semiconductor device comprises a substrate, at least one field effect transistor provided on the substrate, and at least one level shift diode provided on the substrate, where the level shift diode comprises a first layer made of a first compound semiconductor and a second layer made of a second compound semiconductor having an electron affinity smaller than that of the first compound semiconductor. The first and second layers form a heterojunction therebetween. The first and second compound semiconductors are both made of either one of n-type and i-type (or either one of p-type and i-type) semiconductors, and the first layer is used in common with the field effect transistor as a layer of the field effect transistor.

Abstract: A semiconductor device having a high switching speed and high current gain in the microwave region. A semi-metal base transistor is provided to reduce the energy difference between the conduction band edge of a base layer and the valance band edge of an emitter layer or a collector layer, and to reduce the base resistance.

Abstract: A constant current semiconductor device includes a first semiconductor active layer and a second semiconductor active layer which is of a different material from the first active layer and forms a heterojunction together with the first active layer. An intervalley energy difference .DELTA.E.sub.1 of the first active layer which is a difference in energy between bottoms of L and .GAMMA. valleys of the conduction band of the first active layer, is different from an intervalley energy difference .DELTA.E.sub.2 of the second active layer which is a difference in energy between bottoms of L and .GAMMA. valleys of the conduction band of the second active layer. A current saturating voltage at which a current passing through the semiconductor devce is saturated, is set so as to be equal to or greater then .DELTA.E.sub.2 /e, where e is an absolute value of charge of an electron.