Abstract: A rotation detecting device includes a rotation operation part configured to be rotationally operated, a first detector configured to detect a rotation of the rotation operation part and output a first rotation detection signal, a second detector configured to output a second rotation detection signal, with a predetermined phase difference with respect to the first rotation detection signal, a third detector configured to output a third rotation detection signal, with each of a predetermined phase difference with respect to the first rotation detection signal of the first detector and a phase difference with respect to the second rotation detection signal of the second detector, and a controller configured to, based on the first rotation detection signal, the second rotation detection signal, and the third rotation detection signal, perform detection of a failure of the first detector, the second detector, or the third detector.

Abstract: A rotation detecting device includes a rotation operation part configured to be rotationally operated, a first detector configured to detect a rotation of the rotation operation part and output a first rotation detection signal, a second detector configured to output a second rotation detection signal, with a predetermined phase difference with respect to the first rotation detection signal, a third detector configured to output a third rotation detection signal, with each of a predetermined phase difference with respect to the first rotation detection signal of the first detector and a phase difference with respect to the second rotation detection signal of the second detector, and a controller configured to, based on the first rotation detection signal, the second rotation detection signal, and the third rotation detection signal, perform detection of a failure of the first detector, the second detector, or the third detector.

Abstract: A controller of a touch-type input device updates baselines when capacitances of capacitors of a touch panel all remain within a predetermined capacitance range over a predetermined period.

Abstract: A touch-type input device includes a touch panel in which drive electrodes and sensor electrodes are arranged in a grid pattern that provide capacitors. The touch-type input device also includes a controller that determines whether or not there is a touch based on data values that each indicate an amount of change in capacitance of each capacitor from a predetermined reference value. The controller sets the reference value by obtaining a parasitic capacitance of each capacitor when the touch-type input device is activated. When determining from a variation range of the parasitic capacitances of the capacitors that an erroneous reference value has been obtained, the controller re-obtains a parasitic capacitance.

Abstract: A touch-type input device includes a touch panel including drive electrodes and sensor electrodes. Capacitors are formed at intersections of the drive electrodes and sensor electrodes. A controller determines whether a conductive foreign matter exists on the touch panel from raw data values indicating changes in the capacitances of the capacitors from initial reference values. The controller determines touching of the touch panel from control data values indicating changes in the capacitances of the capacitors from control reference values changed when a conductive foreign matter exists. When the raw data values indicate existence of a conductive foreign matter, the controller sets the control reference value of each capacitor to a raw data reference value corresponding to the present raw data value. The controller updates the initial reference value when the touch-type input device is activated and updates the control reference value when the control reference value is erroneous.

Abstract: A controller of a touch-type input device updates baselines when capacitances of capacitors of a touch panel all remain within a predetermined capacitance range over a predetermined period.

Abstract: A touch-type input device includes a touch panel in which drive electrodes and sensor electrodes are arranged in a grid pattern that provide capacitors. The touch-type input device also includes a controller that determines whether or not there is a touch based on data values that each indicate an amount of change in capacitance of each capacitor from a predetermined reference value. The controller sets the reference value by obtaining a parasitic capacitance of each capacitor when the touch-type input device is activated. When determining from a variation range of the parasitic capacitances of the capacitors that an erroneous reference value has been obtained, the controller re-obtains a parasitic capacitance.

Abstract: A touch-type input device includes a touch panel including drive electrodes and sensor electrodes. Capacitors are formed at intersections of the drive electrodes and sensor electrodes. A controller determines whether a conductive foreign matter exists on the touch panel from raw data values indicating changes in the capacitances of the capacitors from initial reference values. The controller determines touching of the touch panel from control data values indicating changes in the capacitances of the capacitors from control reference values changed when a conductive foreign matter exists. When the raw data values indicate existence of a conductive foreign matter, the controller sets the control reference value of each capacitor to a raw data reference value corresponding to the present raw data value. The controller updates the initial reference value when the touch-type input device is activated and updates the control reference value when the control reference value is erroneous.

Abstract: A memory device (103) includes a memory device controller (140), a delay adjustment storage unit (170) configured to store timing adjustment data which is read as both values 0 and 1 at a rise and a fall of a strobe signal, a memory cell (174), and a selector (172) configured to switch connection to the delay adjustment storage unit or the memory cell. A memory interface (102) reads the timing adjustment data of the delay adjustment storage unit (170) while changing the timing to search for a read timing range, and selects and sets read timing from the timing range.

Abstract: The memory interface includes: a first data latch unit that delays a strobe signal from a memory device, through a first variable delay unit and reads the strobe signal as a first data signal; and a second data latch unit that delays the same strobe signal through the second variable delay unit and reads the strobe signal as a second data signal. The memory interface uses the data read by the first data latch unit in a normal memory access operation, detects a boundary of the delay amount by comparing the data with the data read by the second data latch unit, and reflects the boundary on the delay amount of the first variable delay unit. Thereby, the delay amount can be corrected without suspending the normal memory access operation.

Abstract: A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).

Abstract: A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.

Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Abstract: A memory device (103) includes a memory device controller (140), a delay adjustment storage unit (170) configured to store timing adjustment data which is read as both values 0 and 1 at a rise and a fall of a strobe signal, a memory cell (174), and a selector (172) configured to switch connection to the delay adjustment storage unit or the memory cell. A memory interface (102) reads the timing adjustment data of the delay adjustment storage unit (170) while changing the timing to search for a read timing range, and selects and sets read timing from the timing range.

Abstract: A clock enable (CKE) control circuit (112) is provided between a memory control circuit (111) and a SDRAM (120). When a system is in, e.g., a sleep state, the CKE control circuit (112) controls a CKE signal outputted to the SDRAM (120) such that it is fixed to a Low level. As a result, it is possible to halt a power supply provided to the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120), so that power consumption resulting from a leakage current is suppressed. In addition, it becomes also possible to reset the memory control circuit (111), while maintaining the low-power-consumption mode of the SDRAM (120).

Abstract: A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: A transmission cancellation section is provided on a bus connecting a master and a slave. During a reset of the master, the transmission cancellation section blocks the bus so that an invalid command flowing on the bus does not reach the slave and executes, instead of the master stopped by the reset operation, generation of data which corresponds to an access request command already output to the slave and is to be sent to the slave and receiving of data from the slave.

Abstract: A rendering device according to the present invention comprises an information acquiring unit for acquiring system information or rendering object information, a control point generating section for setting a curved surface interpolating level serving to determine number of control points for creating a curved surface or a curved line based on the acquired information and thereby generating the control point in accordance with the curved surface interpolating level, and a curved surface creating section for creating the curved surface based on the control point, wherein an operation quantity for rendering the curved surface of a display object is dynamically changed based on the acquired information.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.