Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: An access request arbitration section, a data amount management section and a resource control section are provided between a plurality of masters and a shared resource. The data amount management section manages access data amounts passing between the plurality of masters and the resource. The access request arbitration section executes arbitrary arbitration of issuing access permission to a master determined according to the access data amount at any timing, in addition to periodic arbitration of issuing access permission to any of the masters at fixed-interval arbitration timing. If an access request of less than a defined data amount is granted in periodic arbitration, the remaining access chance can be used in arbitrary arbitration.

Abstract: A bus arbitration section and a resource control section are interposed between a shared resource and a plurality of bus masters. The minimum number of receivable access permissions within a given period is set as bus arbitration information for each of the bus masters. If two or more of the bus masters issue access requests at the same time, the bus arbitration section preferentially gives access permission to a bus master which gained access permission a number of times less than a set value in the bus arbitration information within the given period, out of the two or more access bus masters.

Abstract: A bus arbitration part for arbitrating access requests from bus masters includes an arbitration history management section that records absence of an access request from any bus master at a given basic arbitration timing. Based on this record, an access request arbitration section issues access permission for an access request issued after the given basic arbitration timing without a wait for the next basic arbitration timing.

Abstract: A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Abstract: To manage accesses from a plurality of masters to a shared resource, a plurality of command registers of each holding an access command received from any of the masters and a plurality of address registers of each holding a register number identifying a command register holding a valid access command, are provided. To rearrange the issuing order of access commands, register numbers held in the address registers are rearranged.

Abstract: Bandwidth information including a plurality of slots each having highest priority order information for arbitrating access conflict, and priority master information for specifying, as a priority master, one or more of a plurality of masters whose latency in accessing a memory serving as a shared resource is desired to be reduced are included as arbitration information. When an arbitration section arbitrates access conflict while switching the slots in the bandwidth information at each of predetermined arbitration timings, if there is an access request from the priority master specified in the priority master information, the arbitration section changes the sequence of the slots in the bandwidth information so as to allow the priority master to access the memory with priority.

Abstract: A rendering device according to the present invention comprises an information acquiring unit for acquiring system information or rendering object information, a control point generating section for setting a curved surface interpolating level serving to determine number of control points for creating a curved surface or a curved line based on the acquired information and thereby generating the control point in accordance with the curved surface interpolating level, and a curved surface creating section for creating the curved surface based on the control point, wherein an operation quantity for rendering the curved surface of a display object is dynamically changed based on the acquired information.

Abstract: Processing is executed by using transistors having a low threshold voltage in a general operation and by using transistors having a high threshold voltage in a standby operation or the like, so as to attain both a high speed operation and a low leakage current. An MPU includes a first MPU constructed from transistors having a high threshold voltage and a second MPU constructed from transistors having a low threshold voltage. When an MPU switching instruction appears on a given instruction stream, data of the first MPU is saved in an external memory section, this data is transferred to the second MPU after switching the control to the second MPU, and the first MPU is disconnected from power by a power control section. Also, when the general operation is switched to the standby operation, the second MPU is switched to the first MPU in the reverse sequence.

Abstract: A resource management apparatus comprises an information selection unit having an operation speed different to an operation speed of a common resource and selecting from information transferred from a plurality of bus masters, a buffer unit for storing the information selected by the information selection unit, and a timing adjustment unit for controlling timings of the information selections in the information selection unit. The information selection unit selects the information comprised of a command and data transferred from any of the plurality of bus masters to the common resource. The timing adjustment unit controls the timings of the information selections in the information selection unit so that the sum of time required for selecting a plurality of predetermined volumes of information in the information selection unit and the sum of processing time in the common resource are substantially equal to each other.

Abstract: A resource management device of the present invention, used in a system where at least one bus master is connected to each of a plurality of buses, includes: a bus arbitration section for arbitrating an amount of access to be made from the buses to a shared resource; an arbitration information management section for managing, as bus arbitration information, a bus priority order and a highest access priority pattern for ensuring a predetermined access bandwidth to the shared resource for each bus for an arbitration operation by the bus arbitration section; and a resource control section for controlling, based on characteristics of the shared resource, an access to the shared resource from the bus whose access request has been granted by the bus arbitration section. Thus, it is possible to guarantee a minimum bandwidth for access to the shared resource for each of the plurality of bus masters.

Abstract: A simulation executing unit includes a conversion unit and a simulation portion. The conversion unit includes a circuit dividing portion, a circuit converting portion and a converted logic circuit generating portion, and the circuit dividing portion divides a logic circuit into combinational partial circuits each interposed between registers or between a register and an input pin or the like. The circuit converting portion generates, on the basis of the divided combinational partial circuits, a converted logic circuit by modifying allocation of registers included in the logic circuit, so as to decrease the number of registers included in the logic circuit without changing the output timing of the logic circuit. The simulation unit performs a simulation on the converted logic circuit.

Abstract: By means of tables, characters, and the like displayed on the screen of a CRT monitor, a functional diagram editor element can generate, on the screen of the CRT monitor, a functional diagram for representing the operation of a logic circuit. A functional diagram check element detects the presence or absence of a contradiction in the generated functional diagram. Furthermore, a functional simulation element can perform the functional verification of the functional diagram free from contradiction. A hardware-description-language conversion element can generate a hardware description language from the functional diagram in which the circuit operation has undergone error correction. A logic synthesis element can generate netlist information from said hardware description language.