Patents by Inventor Yuji Takaoka
Yuji Takaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10014248Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.Type: GrantFiled: June 5, 2015Date of Patent: July 3, 2018Assignee: SONY CORPORATIONInventors: Makoto Murai, Yuji Takaoka, Hiroyuki Yamada, Kazuki Sato, Makoto Imai
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Publication number: 20170239878Abstract: To prevent wear powder from adhering to a film, an expander roller (21) is used that extends in the width direction of a porous film (F) and that is configured to apply a tension to the porous film (F) in the width direction, and foreign matter adhering to the expander roller (21) is removed from a portion of the outer peripheral surface of the expander roller (21) at which portion the expander roller (21) is in no contact with the porous film (F).Type: ApplicationFiled: February 16, 2017Publication date: August 24, 2017Inventors: Koichiro WATANABE, Yuji TAKAOKA
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Publication number: 20170162493Abstract: Provided is a semiconductor device that includes a semiconductor chip, and a packaging substrate on which the semiconductor chip is mounted. The semiconductor chip includes a chip body and a plurality of solder-including electrodes that are provided on an element-formation surface of the chip body. The packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The aperture has a planar shape elongated in a lengthwise direction of the wiring inside the aperture, with a length of the aperture adjusted in accordance with a thermal expansion coefficient of the packaging substrate.Type: ApplicationFiled: June 5, 2015Publication date: June 8, 2017Inventors: MAKOTO MURAI, YUJI TAKAOKA, HIROYUKI YAMADA, KAZUKI SATO, MAKOTO IMAI
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Publication number: 20170148760Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and one or more conductive layers and a solder resist layer that are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the one or more conductive layers, and has one or more apertures on each of the one or more conductive layers. The plurality of solder-including electrodes include two or more first electrodes having a same function other than a function of power supply. The one or more conductive layers include a continuous first conductive layer. The two or more first electrodes are connected to the continuous first conductive layer. The one or more apertures are confronted with the respective two or more first electrodes.Type: ApplicationFiled: June 5, 2015Publication date: May 25, 2017Inventors: MAKOTO MURAI, KAZUKI SATO, HIROYUKI YAMADA, YUJI TAKAOKA, MAKOTO IMAI, SHIGEKI AMANO
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Publication number: 20170141065Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, and a plurality of wirings and a solder resist layer that are provided on a front surface of the substrate body. The plurality of solder-including electrodes include a plurality of first electrodes and a plurality of second electrodes. The plurality of first electrodes supply a first electric potential, and the plurality of second electrodes supply a second electric potential different from the first electric potential. The plurality of first electrodes and the plurality of second electrodes are disposed alternately in both a row direction and a column direction, in a central part of the chip body. The plurality of wirings include a plurality of first wirings and a plurality of second wirings.Type: ApplicationFiled: June 5, 2015Publication date: May 18, 2017Inventors: MAKOTO MURAI, YUJI TAKAOKA, KAZUKI SATO, HIROYUKI YAMADA
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Publication number: 20170141064Abstract: A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging substrate includes a substrate body, a plurality of wirings, and a solder resist layer, in which the plurality of wirings and the solder resist layer are provided on a front surface of the substrate body. The solder resist layer is provided as a continuous layer on the front surface of the substrate body and the plurality of wirings, and has an aperture on each of the plurality of wirings. The plurality of solder-including electrodes include at least one gap control electrode. The at least one gap control electrode includes a columnar metal layer and a solder layer in order named from side on which the chip body is disposed, and includes an overlap region where the columnar metal layer and the solder resist layer overlap each other, along part or all of an aperture end of the aperture.Type: ApplicationFiled: June 5, 2015Publication date: May 18, 2017Inventors: MAKOTO MURAI, YUJI TAKAOKA
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Publication number: 20170092912Abstract: A desired drying capability is achieved while damage to a film is prevented. A film production method is arranged such that: a production process including a drying step is operated by setting a drying condition, under which to carry out the drying step, for each of at least two periods, the two periods being a first period and a second period later than the first period; the drying condition is changed in at least a part of the first period so as to be enhanced with time; and the drying condition is maintained in the second period so as to be substantially fixed.Type: ApplicationFiled: September 28, 2016Publication date: March 30, 2017Inventors: Akihiko SHIN, Yuji TAKAOKA, Atsushi NAKAZAWA, Hideyuki SASAKI
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Publication number: 20160276385Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: ApplicationFiled: May 27, 2016Publication date: September 22, 2016Inventors: Yoshihiro Nabe, Hiroshi ` Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 9379155Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: GrantFiled: April 17, 2015Date of Patent: June 28, 2016Assignee: Sony CorporationInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Publication number: 20150221690Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: ApplicationFiled: April 17, 2015Publication date: August 6, 2015Inventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 9041179Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: GrantFiled: March 6, 2014Date of Patent: May 26, 2015Assignee: SONY CORPORATIONInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Publication number: 20140183680Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: ApplicationFiled: March 6, 2014Publication date: July 3, 2014Applicant: Sony CorporationInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 8564101Abstract: A semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has another insulating layer formed in the via hole and a conductive layer formed thereon. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.Type: GrantFiled: January 6, 2009Date of Patent: October 22, 2013Assignees: Sony Corporation, Fujikura Ltd.Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
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Publication number: 20120286387Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: ApplicationFiled: July 19, 2012Publication date: November 15, 2012Applicant: SONY CORPORATIONInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Patent number: 8273657Abstract: A method for manufacturing a semiconductor apparatus having a through-hole interconnection in a semiconductor substrate. An insulating layer is formed on the semiconductor substrate. A via hole is formed through the semiconductor substrate and the insulating layer. Another insulating layer is formed in the via hole, and a conductive layer of the through-hole interconnection is subsequently formed. The insulating layer formed in the via hole is formed such as to substantially planarize an inner surface of the via hole.Type: GrantFiled: February 15, 2011Date of Patent: September 25, 2012Assignees: Sony Corporation, Fujikura Ltd.Inventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
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Patent number: 8252628Abstract: A semiconductor device includes a semiconductor substrate having first and second surfaces opposite each other, the first surface being an active surface by provided with an electronic element thereon, a pad electrode formed to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening, formed to reach the pad electrode from a bottom surface of the first opening, having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: GrantFiled: March 12, 2008Date of Patent: August 28, 2012Assignee: Sony CorporationInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
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Publication number: 20110136342Abstract: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.Type: ApplicationFiled: February 15, 2011Publication date: June 9, 2011Applicants: SONY CORPORATION, FUJIKURA LTDInventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
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Patent number: 7851880Abstract: A solid-state imaging device includes a semiconductor substrate having a foreside provided with an imaging area and an electrode pad, the imaging area having an array of optical sensors, the electrode pad being disposed around a periphery of the imaging area; a transparent substrate joined to the foreside of the semiconductor substrate with a sealant therebetween; underside wiring that extends through the semiconductor substrate from the electrode pad to an underside of the semiconductor substrate; and a protective film composed of an inorganic insulating material and interposed between the semiconductor substrate and the sealant, the protective film covering at least the electrode pad.Type: GrantFiled: November 26, 2007Date of Patent: December 14, 2010Assignee: Sony CorporationInventors: Masami Suzuki, Yoshimichi Harada, Yoshihiro Nabe, Yuji Takaoka, Masaaki Takizawa, Chiaki Sakai
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Publication number: 20090200679Abstract: A semiconductor apparatus including a semiconductor substrate, an insulating layer, a via hole, and a through-hole interconnection is provided. The insulating layer is formed on the semiconductor substrate. The via hole is formed through the semiconductor substrate and the insulating layer. The through-hole interconnection has a conductive layer formed on an insulating layer in the via hole. The surface of the insulating layer formed on the inner surface of the via hole is substantially planarized by filling a recessed portion on a boundary between the semiconductor substrate and the insulating layer formed on the semiconductor substrate.Type: ApplicationFiled: January 6, 2009Publication date: August 13, 2009Applicants: SONY CORPORATION, FUJIKURA LTDInventors: Yoshimichi Harada, Masami Suzuki, Yoshihiro Nabe, Yuji Takaoka, Tatsuo Suemasu, Hideyuki Wada, Masanobu Saruta
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Publication number: 20080224249Abstract: A semiconductor device includes a semiconductor substrate having first and second surfaces opposite each other, the first surface being an active surface by provided with an electronic element thereon, a pad electrode formed to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening, formed to reach the pad electrode from a bottom surface of the first opening, having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.Type: ApplicationFiled: March 12, 2008Publication date: September 18, 2008Applicant: SONY CORPORATIONInventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada