Abstract: A semiconductor device includes a first main electrode, a second main electrode, and a semiconductor layer. The semiconductor layer includes a p-type semiconductor region disposed at a position exposed from the upper surface of the semiconductor layer and electrically connected to the second main electrode, and an n-type semiconductor region in contact with the p-type semiconductor region and separated from the second main electrode by the p-type semiconductor region. The n-type semiconductor region has a trap region provided at a position in contact with the p-type semiconductor region, and a hole trap is formed in the trap region.

Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

Abstract: A switching element includes a semiconductor substrate, a gate insulating film, and a gate electrode that is disposed inside the trench. The semiconductor substrate further includes: an n-type source region, a p-type body region, an n-type drift region, a p-type first electric field reduced region, and a p-type connection region. When a permittivity of the connection region is ? (F/cm), a critical electric field strength of the connection region is Ec (V/cm), an elementary charge is e (C), an area density of p-type impurity when viewed in a plan view of the connection region located below the trench is Q (cm?2), Q>?*Ec/e.

Abstract: A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate that has a front surface and a rear surface; and a plurality of ohmic electrodes that are in ohmic contact with a surface of silicon carbide on at least one of the front surface and the rear surface of the silicon carbide semiconductor substrate. The plurality of ohmic electrodes are scattered on the surface of the silicon carbide to provide a concavity and convexity. The concavity and convexity has a height due to the ohmic electrodes less than 1.0 ?m.

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

Abstract: A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate that has a front surface and a rear surface; and a plurality of ohmic electrodes that are in ohmic contact with a surface of silicon carbide on at least one of the front surface and the rear surface of the silicon carbide semiconductor substrate. The plurality of ohmic electrodes are scattered on the surface of the silicon carbide to provide a concavity and convexity. The concavity and convexity has a height due to the ohmic electrodes less than 1.0 ?m.

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.

Abstract: A semiconductor device includes an inversion type semiconductor element including: a semiconductor substrate; a first conductive type layer formed on the semiconductor substrate; an electric field blocking layer formed on the first conductive type layer and including a linear shaped portion; a JFET portion formed on the first conductive type layer and having a linear shaped portion; a current dispersion layer formed on the electric field blocking layer and the JFET portion; a deep layer formed on the electric field blocking layer and the JFET portion; a base region formed on the current dispersion layer and the deep layer; a source region formed on the base region; trench gate structures including a gate trench, a gate insulation film, and a gate electrode, and arranged in a stripe shape; an interlayer insulation; a source electrode; and a drain electrode formed on a back surface side of the semiconductor substrate.

Abstract: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.

Abstract: A silicon carbide semiconductor device includes: a main cell region; a sense cell region; a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate having a high impurity concentration layer and a drift layer; an element isolation layer arranged between the main cell region and the sense cell region, and surrounding the sense cell region; and a plurality of electric field relaxation layers arranged between the main cell region and the sense cell region. The MOSFET includes: a base region; a source region; a plurality of deep layers; a trench gate structure; a source electrode; and a drain electrode. The deep layers and the electric field relaxation layers are arranged in a stripe pattern at a predetermined interval.

Abstract: Intervals of the frame portion and the p type guard ring on a cell portion side are made narrower than other parts, and the narrowed part provides a dot line portion. By narrowing the intervals of the frame portion and the p type guard ring on the cell portion side, the electric field concentration is reduced on the cell portion side, and the equipotential line directs to more outer circumferential side. By providing the dot line portions, the difference in the formation areas of the trench per unit area in the cell portion, the connection portion and the guard ring portion is reduced, and the thicknesses of the p type layers formed on the cell portion, the connection portion and the guard ring portion are uniformed. Thereby, when etching-back the p type layer, the p type layer is prevented from remaining as a residue in the guard ring portion.

Abstract: All of intervals between adjacent p type guard rings are set to be equal to or less than an interval between p type deep layers. As a result, the interval between the p type guard rings becomes large, i.e., the trenches are formed sparsely, so that the p type layer is prevented from being formed thick at the guard ring portion when the p type layer is epitaxially grown. Therefore, by removing the p type layer in the cell portion at the time of the etch back process, it is possible to remove the p type layer without leaving any residue in the guard ring portion. Therefore, when forming the p type deep layer, the p type guard ring and the p type connection layer by etching back the p type layer, the residue of the p type layer is restricted from remaining in the guard ring portion.

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

Abstract: A silicon carbide semiconductor device includes: a main cell region; a sense cell region; a MOSFET arranged in each of the main cell region and the sense cell region and disposed in a semiconductor substrate having a high impurity concentration layer and a drift layer; an element isolation layer arranged between the main cell region and the sense cell region, and surrounding the sense cell region; and a plurality of electric field relaxation layers arranged between the main cell region and the sense cell region. The MOSFET includes: a base region; a source region; a plurality of deep layers; a trench gate structure; a source electrode; and a drain electrode. The deep layers and the electric field relaxation layers are arranged in a stripe pattern at a predetermined interval.

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

Abstract: A method of manufacturing a switching device may include: forming a plurality of trenches in an upper surface of a semiconductor substrate, the plurality of trenches extending in parallel to each other at the upper surface; forming a mask including a masking portion and an opening portion, the masking portion and the opening portion being arranged on each of the trenches alternately and repeatedly along a longitudinal direction of the trenches; and implanting p-type impurities to a bottom surface of each of the trenches through the mask so as to form a plurality of bottom p-type regions.