Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.

Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

Abstract: An n-type drift region, a p-type first body region and a p-type contact region are formed on an SiC substrate by epitaxial growth. An opening is formed within the contact region by etching such that the first body region is exposed through the opening, and a p-type second body region is formed on the first body region exposed through the opening by epitaxial growth. An n-type source region is formed by epitaxial growth, and an opening is formed within a part of the source region located on the contact region by etching such that the contact region is exposed through the opening. A trench is formed by etching such that the trench extends from the source region to the drift region through the opening of the contact region, and a gate insulating film and a gate electrode are formed within the trench.

Abstract: A method for manufacturing an insulated gate switching device is provided. The method includes: forming a first trench in a surface of a first SiC semiconductor layer; implanting p-type impurities into a bottom surface of the first trench; depositing a second SiC semiconductor layer on an inner surface of the first trench to form a second trench; and forming a gate insulating layer, a gate electrode, a first region and a body region so that the gate insulating layer covers an inner surface of the second trench, the gate electrode is located in the second trench, the first region is of n-type and in contact with the gate insulating layer, the body region is of p-type, separated from the implanted region, and in contact with the gate insulating layer under the first region.

Abstract: A semiconductor device includes a semiconductor substrate configured such that a trench is provided on a surface of the semiconductor substrate at a position of at least one of a boundary region disposed between a field-effect transistor region and a diode region, a boundary region disposed between the diode region and a peripheral voltage withstanding region, and a boundary region disposed between the field-effect transistor region and the peripheral voltage withstanding region; an insulating film covering an inner surface of the trench; and an electrode film covering an inner surface of the insulating film, the electrode film being configured to be electrically connected to one of a source electrode and an anode electrode.

Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.

Abstract: In a plane view of the front surface of the semiconductor substrate, the source region and the first contact region are arranged adjacent to each other in a direction along the gate trench in an area being in contact with a side surface of the gate trench, and the second contact region is arranged adjacent to the source region and the first contact region in an area apart from the gate trench. The impurity concentration of the first contact region is lower than the impurity concentration of the second contact region.

Abstract: A switching device includes first-third semiconductor layers, a gate insulating film, and a gate electrode. The first semiconductor layer is of a first conductivity type. The second semiconductor layer is of a second conductivity type and in contact with the first semiconductor layer. The third semiconductor layer is of the first conductivity type, in contact with the second semiconductor layer. The gate insulating film covers a surface of the second semiconductor layer in a range in which the second semiconductor layer separates the first semiconductor layer from the third semiconductor layer. The gate electrode faces the second semiconductor layer via the gate insulating film. The gate electrode includes a fourth semiconductor layer covering a surface of the gate insulating film; and a fifth semiconductor layer having a bandgap different from a bandgap of the fourth semiconductor layer and covering a surface of the fourth semiconductor layer.

Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.

Abstract: A Schottky barrier diode provided herein includes: a semiconductor substrate; and an anode electrode being in contact with the semiconductor substrate. The semiconductor substrate includes: p-type contact regions being in contact with the anode electrode; and an n-type drift region being in contact with the anode electrode by Schottky contact in a range where the p-type contact regions are not provided The p-type contact regions includes: a plurality of circular regions located so that the circular regions are arranged at intervals between an outer side and an inner side at a contact surface between the semiconductor substrate and the anode electrode; and an internal region located in an inner portion of the circular region located on an innermost side at the contact surface and connected to the circular region located on the innermost side at the contact surface.

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

Abstract: The bottom surface of the trench is provided so that a center part of the bottom surface protrudes upward with respect to a peripheral part of the bottom surface in a short direction. A thickness of the gate insulating film covering the peripheral part is thicker than a thickness of the gate insulating film covering the center part.

Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.

Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

Abstract: A switching circuit disclosed, herein, includes a main MOSFET 12, a control MOSFET 14, and a diode 16. The main MOSFET is formed in a SiC semiconductor layer. A channel type of the main MOSFET is a first conductivity type. A channel type of the control MOSFET is a second conductivity type. A source of the control MOSFET is connected to-a gate of the main MOS-FET. A cathode of the diode is connected to a gate of one of the main MOSFET and the control MOSFET. An anode of the diode is connected to a gate of the other of the main MOSFET and the control MOSFET. A channel type of the one is an n-type. A channel type of the other is a p-type.

Abstract: A switching device includes first-third semiconductor layers, a gate insulating film, and a gate electrode. The first semiconductor layer is of a first conductivity type, The second semiconductor layer is of a second conductivity type and in contact with the first semiconductor layer. The third semiconductor layer is of the first conductivity type, in contact with the second semiconductor layer. The gate insulating film covers a surface of the second semiconductor layer in a range in which the second semiconductor layer separates the first semiconductor layer from the third semiconductor layer. The gate electrode faces the second semiconductor layer via the gate insulating film. The gate electrode includes a fourth semiconductor layer covering a surface of the gate insulating film; and a fifth semiconductor layer having a bandgap different from a bandgap of the fourth semiconductor layer and covering a surface of the fourth semiconductor layer.

Abstract: In a silicon carbide semiconductor device, a p-type SiC layer is disposed in a corner of a bottom of a trench. Thus, even if an electric field is applied between a drain and a gate when a MOSFET is turned off, a depletion layer in a pn junction between the p-type SiC layer and an n? type drift layer greatly extends toward the n? type drift layer, and a high voltage caused by an influence of a drain voltage hardly enters a gate insulating film. Hence, an electric field concentration within the gate insulating film can be reduced, and the gate insulating film can be restricted from being broken. In this case, although the p-type SiC layer may be in a floating state, the p-type SiC layer is formed in only the corner of the bottom of the trench. Thus, the deterioration of the switching characteristic is relatively low.