Patents by Inventor Yukio Hashimoto

Yukio Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230305648
    Abstract: An input device includes two fixed electrodes and an operating member. The two fixed electrodes is configured to be placed to overlap with specific line electrodes of a plurality of line electrodes . The operating member is movable with respect to the two fixed electrodes. The operating member is movable within a movable range including a plurality of click points. Electrical states of the two fixed electrodes change among a plurality of states in accordance with a movement of the operating member. A divisor of an integer N does not include 4, where the integer N is a total number of times of change in the electrical states of the at least two fixed electrodes when the operating member moves from one to a next one of adjacent two click points of the plurality of click points.
    Type: Application
    Filed: January 29, 2021
    Publication date: September 28, 2023
    Inventors: Kota ARAKI, Hiroaki NISHIONO, Sohui JEON, Takumi NISHIMOTO, Yukio HASHIMOTO
  • Patent number: 9496236
    Abstract: A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: November 15, 2016
    Assignee: Tessera, Inc.
    Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Wills Mirkarimi, Rajesh Katkar
  • Patent number: 8957520
    Abstract: A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.
    Type: Grant
    Filed: June 8, 2011
    Date of Patent: February 17, 2015
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Yukio Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Publication number: 20150014850
    Abstract: A microelectronic assembly includes first and second surfaces, a first thin conductive element, a first conductive projection, and a first fusible mass. The first thin conductive element includes a face that has first and second regions. The first conductive projection covers the first region of the first face. A barrier may be formed along a portion of the first region. The second face includes a second conductive projection that extends away therefrom. The first fusible metal mass connects the first conductive projection to the second conductive projection such that the first surface of the first face is oriented toward the second surface of the second substrate. The first mass extends along a portion of the first conductive projection to a location toward the first edge of the barrier. The barrier is disposed between the first thin element and the first metal mass.
    Type: Application
    Filed: September 30, 2014
    Publication date: January 15, 2015
    Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Wills Mirkarimi, Rajesh Katkar
  • Patent number: 8853558
    Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: October 7, 2014
    Assignee: Tessera, Inc.
    Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
  • Patent number: 8736064
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 27, 2014
    Assignee: Invensas Corporation
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Patent number: 8490265
    Abstract: A brake includes an annular boot which can be expanded and contracted according to movements of a piston and is assembled to an opening part of a cylinder and to an annular groove on an outer peripheral face of the piston. The boot is assembled by: engaging one end of the boot with the opening part of the cylinder in a state where the piston is contained in the cylinder; moving the piston so that at least a part of the piston is withdrawn from the cylinder and that the other end of the boot is pressed by a pressing face of the piston; and fitting the other end of the boot into the annular groove of the piston, while a movable range of the other end of the boot is restricted by an expanding allowance of the boot whose one end is engaged with the opening part of the cylinder.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: July 23, 2013
    Assignee: Akebono Brake Industry Co., Ltd.
    Inventors: Yukio Hashimoto, Masayoshi Kojima, Katsunori Kinno, Mitsuru Sato
  • Publication number: 20120313238
    Abstract: A microelectronic assembly may include a substrate containing a dielectric element having first and second opposed surfaces. The dielectric element may include a first dielectric layer adjacent the first surface, and a second dielectric layer disposed between the first dielectric layer and the second surface. A Young's modulus of the first dielectric layer may be at least 50% greater than the Young's modulus of the second dielectric layer, which is less than two gigapascal (GPa). A conductive structure may extend through the first and second dielectric layers and electrically connect substrate contacts at the first surface with terminals at the second surface. The substrate contacts may be joined with contacts of a microelectronic element through conductive masses, and a rigid underfill may be between the microelectronic element and the first surface. The terminals may be usable to bond the microelectronic assembly to contacts of a component external to the microelectronic assembly.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Hiroaki Sato, Yukio Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Publication number: 20120286416
    Abstract: A microelectronic assembly may include a microelectronic element having a plurality of element contacts at a face thereof, and a compliant dielectric element having a Young's modulus of less than about two gigapascal (GPa) and substrate contacts at a first surface joined to the element contacts. The substrate contacts may be electrically connected with terminals at a second surface of the compliant dielectric element that opposes the first surface, through conductive vias in the compliant dielectric element. A rigid underfill may be between the face of the microelectronic element and the first surface of the compliant dielectric element. The terminals may be usable for bonding the microelectronic assembly to corresponding contacts of a component external to the microelectronic assembly.
    Type: Application
    Filed: May 11, 2011
    Publication date: November 15, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Hiroaki Sato, Yukio Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Publication number: 20120145442
    Abstract: A microelectronic assembly includes a first surface and a first thin conductive element exposed at the first surface and having a face comprising first and second regions. A first conductive projection having a base connected to and covering the first region of the face extends to an end remote from the base. A first dielectric material layer covers the second region of the first thin element and contacts at least the base of the first conductive projection. The assembly further includes a second substrate having a second face and a second conductive projection extending away from the second face. A first fusible metal mass connects the first projection to the second projection and extends along an edge of the first projection towards the first dielectric material layer.
    Type: Application
    Filed: December 10, 2010
    Publication date: June 14, 2012
    Applicant: TESSERA RESEARCH LLC
    Inventors: Debabrata Gupta, Yukio Hashimoto, Ilyas Mohammed, Laura Mirkarimi, Rajesh Katkar
  • Publication number: 20110057324
    Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.
    Type: Application
    Filed: November 8, 2010
    Publication date: March 10, 2011
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20090307892
    Abstract: A brake includes an annular boot which can be expanded and contracted according to movements of a piston and is assembled to an opening part of a cylinder and to an annular groove on an outer peripheral face of the piston. The boot is assembled by: engaging one end of the boot with the opening part of the cylinder in a state where the piston is contained in the cylinder; moving the piston so that at least a part of the piston is withdrawn from the cylinder and that the other end of the boot is pressed by a pressing face of the piston; and fitting the other end of the boot into the annular groove of the piston, while a movable range of the other end of the boot is restricted by an expanding allowance of the boot whose one end is engaged with the opening part of the cylinder.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 17, 2009
    Applicant: AKEBONO BRAKE INDUSTRY CO., LTD.
    Inventors: Yukio HASHIMOTO, Masayoshi Kojima, Katsunori Kinno, Mitsuru Sato
  • Patent number: 7407708
    Abstract: A chemically resistant, extractable free, composite laminar film including polyimide, PFA and m-PTFE layers.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: August 5, 2008
    Assignee: Entegris, Inc.
    Inventors: Mutsuhiro Amari, Yukio Hashimoto, Tsutomu Ogawa
  • Publication number: 20080169568
    Abstract: A multilayer interconnect element is provided which includes at least one dielectric element in which metal interconnect patterns are exposed at an outer surface thereof, the metal interconnect patterns having outer surfaces which are co-planar with an exposed outer surface of the dielectric element. In addition, multilayer interconnect elements are provided in which second interconnect elements which do not have co-planar interconnect patterns are integrated therewith as intermediate elements, and the resulting multilayer interconnect element has co-planar interconnect patterns.
    Type: Application
    Filed: August 29, 2007
    Publication date: July 17, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080136041
    Abstract: An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.
    Type: Application
    Filed: May 23, 2007
    Publication date: June 12, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Hideki Kotake, Kiyoshi Hyodo, Inetaro Kurosawa, Yukio Hashimoto, Toku Yoshino, Tomoo Iijima
  • Publication number: 20080128288
    Abstract: Methods are provided for manufacturing a wiring circuit element or wiring board in which a set of rough wiring patterns are formed by selectively etching a metal layer of a patternable member which includes a carrier layer having a rough surface and a thin rough-surfaced etch stop layer between the carrier layer and the metal layer. The etch stop layer and wiring patterns are joined to an insulating layer such that the wiring patterns adhere to the insulating layer and the insulating layer acquires a rough surface. Thereafter, the carrier layer and the etch stop layer are removed, after which openings are formed in the insulating layer in contact with at least some of the wiring patterns. A layer of metal is electrolessly plated onto the rough major surface of the insulating layer, and then a conductive wiring pattern is selectively electroplated over the electrolessly plated layer to form plated openings that interconnect at least some of the wiring patterns.
    Type: Application
    Filed: June 8, 2007
    Publication date: June 5, 2008
    Applicant: Tessera Interconnect Materials, Inc.
    Inventors: Yukio Hashimoto, Inetaro Kurosawa, Hideki Kotake
  • Patent number: 7378114
    Abstract: A method for producing a composition containing soluble isoflavones is described, which uses soybean materials as raw materials. The composition is obtained in a natural state without addition of solubilizing agents and chemical modification, and has high solubility under neutral to acidic conditions and good long-term stability under refrigeration. By removing the insoluble materials from the water-extract liquid of a soybean material having a pH value of 2-7 and a temperature of 0-17° C., a composition containing isoflavones can be efficiently obtained with high solubility under neutral to acidic conditions and good stability under refrigeration.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: May 27, 2008
    Assignee: Fuji Oil Company, Limited
    Inventors: Shinichi Tsuzaki, Hideo Araki, Yukio Hashimoto
  • Patent number: 7262373
    Abstract: A multifunctional switch having a push button placed on an upper surface, and an operating lever protruding laterally from the side thereof. The push button on the upper surface is used to operate a push switch. The operating lever on the side is used to operate a rotary switch.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: August 28, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Seiki Miura, Yukio Hashimoto
  • Publication number: 20070105456
    Abstract: A press-fit fixing terminal is mountable to a wiring board by being inserted into a through-hole of the wiring board, and includes a flat plate section and a resilient contacting section. The flat plate section is made of metal thin plate and double-backed such that an end of the flat plate section is placed on a root side and a bent point works as an insertion tip when the terminal is inserted into the through-hole. The resilient contacting sections sandwich the double-backed portion of the flat plate section such that they are placed symmetrically with respect to the double-backed portion and both of the ridges of the resilient contacting section face outward viewed from the double-backed portion, so that each one of the resilient contacting sections forms a V-shape including an obtuse angle.
    Type: Application
    Filed: August 29, 2006
    Publication date: May 10, 2007
    Inventors: Yukio Hashimoto, Seiki Miura, Takumi Nishimoto, Takashi Tomago
  • Patent number: 7210969
    Abstract: A press-fit fixing terminal is mountable to a wiring board by being inserted into a through-hole of the wiring board, and includes a flat plate section and a resilient contacting section. The flat plate section is made of metal thin plate and double-backed such that an end of the flat plate section is placed on a root side and a bent point works as an insertion tip when the terminal is inserted into the through-hole. The resilient contacting sections sandwich the double-backed portion of the flat plate section such that they are placed symmetrically with respect to the double-backed portion and both of the ridges of the resilient contacting section face outward viewed from the double-backed portion, so that each one of the resilient contacting sections forms a V-shape including an obtuse angle.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 1, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yukio Hashimoto, Seiki Miura, Takumi Nishimoto, Takashi Tomago