Structure and method of making interconnect element having metal traces embedded in surface of dielectric
An interconnect element is provided which includes a dielectric element having a major surface. Metal interconnect patterns are embedded in recesses which extend inwardly from the major surface, the outer surfaces of the interconnect patterns being substantially co-planar with the major surface and extending in one or more directions of the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface such that it contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.
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This application is a continuation of U.S. application Ser. No. 11/541,734, filed Oct. 2, 2006, which is a continuation of U.S. application Ser. No. 11/338,455, filed Jan. 24, 2006, the disclosures of which is hereby incorporated herein by reference. The present application is based upon and claims the benefit of priority from Japanese Patent Application No. 2005-15970, filed Jan. 24, 2005, the disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTIONThe present invention specifically relates to interconnect structures for microelectronics, e.g., in the packaging of microelectronic units such as integrated circuits (“ICS” or “chips”) and other interconnect structures, e.g., circuit panels such as includes printed or other types of wiring boards.
There is a present need to provide interconnect elements having either a single layer or multiple layers of metal interconnect patterns permitting selective interconnection to external circuit elements.
SUMMARY OF THE INVENTIONIn accordance with an aspect of the invention, an interconnect element includes a dielectric element having a major surface. Metal interconnect patterns extending in one or more directions of the major surface are embedded in recesses which extend inwardly from the major surface. Outer surfaces of the interconnect patterns are substantially co-planar with the major surface. A projecting conductive film extends over the major surface in at least one direction parallel to a plane defined by the major surface. The projecting conductive film contacts the dielectric element along at least a portion of the major surface and conductively contacts an outer surface of at least one of the metal interconnect patterns.
In accordance with one or more preferred aspects of the invention, the interconnect element may further include an insulating cover film overlying only a portion of the major surface and at least one of the metal interconnect patterns such that the projecting conductive film is exposed by the insulating cover film.
In accordance with one or more preferred aspects of the invention, at least a portion of the projecting conductive film conductively interconnects respective ones of the metal interconnect patterns.
In accordance with a preferred embodiment of the invention, the major surface is a first major surface, the dielectric element includes a second major surface remote from the first major surface and a plurality of second recesses extend inwardly from the second major surface. In such embodiment, the metal interconnect patterns are first metal interconnect patterns embedded in the first recesses, and the interconnect element further includes a plurality of second metal interconnect patterns which extend in one or more directions of the second major surface. These second metal interconnect patterns are embedded in the second recesses, and have outer surfaces that are substantially co-planar with the second major surface. In addition, at least some of the first metal interconnect patterns are conductively connected to at least some of the second metal interconnect patterns.
In accordance with one or more preferred aspects of the invention, at least some of the first metal interconnect patterns are conductively connected to at least some of the second metal interconnect patterns. Connection is provided by one or more conductors which extend through the dielectric element in a direction transverse to the plane defined by the first major surface of the dielectric element.
Preferably, the one or more conductors extending through the dielectric element includes a conductor lining a through hole extending through the dielectric element.
In a particular aspect of the invention, an assembly includes an interconnect element as specified herein and further includes an external circuit element. An exposed lead of such circuit element is inserted into the through hole in conductive contact with the conductor to provide conductive interconnection to the interconnect element.
In accordance with another preferred aspect of the invention, a solid conductive post extends through the dielectric element which contacts inner surfaces of at least some of the first and second metal interconnect patterns, these inner surfaces being recessed inwardly from the first and second major surfaces of the dielectric element.
In accordance with another preferred aspect of the invention, a first insulating cover film overlies a first portion of the first major surface and at least one of the first metal interconnect patterns, such that the projecting conductive film is exposed by the insulating cover film.
An assembly in accordance with a particular aspect of the invention includes an interconnect element as specified herein and an external circuit element. An exposed contact of the external circuit element is conductively connected to the projecting conductive film of the interconnect element.
Preferably, the projecting conductive film is conductively connected to the contact through an anisotropic conductive film.
In accordance with another aspect of the invention, a method is provided for fabricating an interconnect element. In accordance with such method, a structure is provided which includes a first metal layer overlying a second metal layer. A plurality of metal interconnect patterns are patterned from the first metal layer of the structure after which a dielectric element is formed overlying the metal interconnect patterns of the structure. The second metal layer is then removed selectively to the plurality of metal interconnect patterns, such that the plurality of metal interconnect patterns are embedded in the dielectric element and have outer surfaces co-planar with a first major surface of the dielectric element. A projecting conductive film is formed to extend over the first major surface in at least one direction parallel to a plane defined by the major surface so as to contact the dielectric element along at least a portion of the first major surface and conductively contact an outer surface of at least one of the metal interconnect patterns.
Preferably, the step of forming the dielectric element includes pressing a layer including an uncured resin over the plurality of metal interconnect patterns.
In accordance with a particular aspect of the invention, the metal interconnect patterns are first metal interconnect patterns embedded in first recesses extending inwardly from the first major surface. Preferably, the method further includes providing a second structure including a third metal layer overlying a fourth metal layer and patterning a plurality of second metal interconnect patterns from the third metal layer. The step of forming the dielectric element additionally includes pressing the second structure onto a second major surface of the dielectric element remote from the first major surface. The fourth metal layer is then removed selectively to the plurality of second metal interconnect patterns. In this way, the second metal interconnect patterns are embedded in the second major surface of the dielectric element and the second metal interconnect patterns have outer surfaces co-planar with the second major surface. Further in accordance with such aspect of the invention, a through hole is formed to extend through the dielectric element between the first metal interconnect patterns and the second metal interconnect patterns, and a conductor is formed to line the through hole simultaneously when forming the projecting conductive film, such conductor connecting the first metal interconnect patterns to the second metal interconnect patterns.
According to certain embodiments of the invention, a multilayer interconnect element or multilayer wiring board is provided wherein metal traces of an interconnection layer are embedded within recesses at the surface of a dielectric element. In addition, the metal traces are formed in such manner that they are much less prone to become twisted, or produce shorts with adjacent interconnections, or break, even when the number of interconnect elements joined together is high. In such embodiments, the surface of each interconnect element presents a substantially planar major surface having conductive contacts thereon for interconnection with other microelectronic elements. In this way, the metal traces do not protrude in ways which interfere with mounting electronic components. Also, improved reliability of the electrical connections may be achieved between several interconnect elements that make up a multilayer interconnect element or multilayer wiring board having three or more layers on which such embedded metal traces are provided. In addition, it may be possible to achieve a reduction in the manufacturing processes required to fabricate such interconnect elements.
In an interconnect element 22 according to an embodiment of the present invention shown in
Embedded within the dielectric element 20 are first interconnection patterns 12, 12a provided as a first metal wiring layer and second interconnection patterns 13, 13a provided by a second metal wiring layer. Each of the first interconnect patterns and the second interconnect patterns includes a plurality of metal traces and contacts or other metallic interconnect features. The thickness of each metal wiring layer is preferably between about 10 microns and several dozen microns. The contacts and metal traces function to provide conductive interconnection between the interconnect element 22 and other microelectronic elements external thereto and/or between different external microelectronic elements. Such microelectronic elements can be, for example, any of microelectronic substrates, circuit panels, integrated circuits (“ICs” or “chips”), packaged chips, i.e., chips having package elements bonded thereto, whether or not such chips include only active circuit elements, passive circuit elements such as commonly known as “integrated passives on chip” (IPOC) or chips having a combination of active and passive types of circuit elements, among others.
A plurality of solid metal posts 18 extend through the dielectric element 20 between the first interconnect patterns 12 and the second interconnect patterns 13. The posts most preferably include or consist essentially of copper. Preferably the posts include high purity copper. The end-to-end length or “height” of each post within the dielectric element 20 is preferably between, for example, several dozen and about 150 microns. However, the height may be somewhat greater than or less than the stated preferred range.
In a particular embodiment a chip, circuit panel or packaged chip is directly or indirectly conductively interconnected to or bonded to interconnection patterns 12, 12a including traces and contacts exposed at a first major surface 24 of the interconnect element 22. On a second major surface 26 of the interconnect element 22 remote from the first major surface 24, contacts 13, 13a of the interconnect element can be further bonded, directly or indirectly, to a circuit panel, another chip, or package element of another packaged chip. In another embodiment, the metal traces on one or both major surfaces 24, 26 of the interconnect element 22 can be contacted by a packaged chip and maintain conductive communication with the packaged chip under a moderate amount of pressure in which some flexing of the dielectric element 20 may occur as a result of the pressure between the interconnect element and the packaged chip.
In an embodiment of manufacturing a multilayer interconnect element or wiring board, heating to a temperature of, for example, between 150 and 350° C. is suitable, and a pressure between 20 and 100 kg/cm2 is preferred. In addition, it is preferable to coat the metal traces exposed at one or both of the first and second major surfaces 24, 26 with a bond metal, especially when electronic components are to be mounted thereto such as integrated circuits (ICs or chips) that have high numbers of terminals with minute pitches. Gold is well suited for use as the bond metal layer 10.
The details of the present invention will be explained based on an embodiment shown in a figure.
First, a patternable conductive structure 2, made from a three metal layer structure is prepared as shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, referring to
Following this, as shown in
Following this, as shown in
Following this, the first such interconnect structure 2′, having an insulating layer 20 is formed in the state shown in
This joining process connects the metal posts 18 to the interconnect patterns, doing so through metal-to-metal bonding of the posts 18 to the interconnect patterns 13 and 13, especially via copper-to-copper contact. This process integrates the two structures 2 and 2′ into a single unit.
Following this, as shown in
Following this, as shown in
Given this type of method for manufacturing, an interconnect element or wiring board is fabricated wherein the interconnection layer and the insulating layer are co-planar as shown in
As shown in
Note that each of the aforementioned patternable conductive structures 32 have three-layer structures wherein a metal layer 40 for fabricating an interconnection layer including or consisting essentially of copper, for example, overlies an etching barrier layer (an intermediate layer) 34, which includes or consists essentially of a metal that would not be attacked by an etchant which attacks the first metal. For example, when the first metal includes or consists essentially of copper, and the etching barrier layer can include or consist essentially of nickel. Copper can be etched by an etchant which substantially does not attack nickel. In turn, the first metal 40 and the etching barrier layer 34 are provided on or overlying a surface of a carrier layer 36 made from, for example, copper. The patternable conductive structure is preferably fabricated through rolling, although other methods can be used.
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Following this, as is shown in
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Following this, as shown in
Each of the aforementioned interconnection structures 52 and 52 includes an interconnection layer including interconnection patterns 60. The interconnection layer may include or consist essentially of copper, for example. In turn, the interconnection layer overlies an etching barrier layer (an intermediate layer 56), made from, for example, nickel. The etching barrier layer, in turn, overlies a carrier layer 54, made from, for example, copper. Moreover, each of these interconnection structures 52 and 52 are oriented so that the sides whereon the interconnect patterns 60 are formed are facing each of the interlayer insulation layers 50 and 50, and are provided aligned so that the various electrically conductive pillars 48 will be lined up with the corresponding interconnection layers 60.
Following this, as shown in
Following this, as shown in
Following this, the aforementioned carrier layers 54 (
Following this, each of the aforementioned etching barrier layers 58 and 38
This type of method for manufacturing fabricates an interconnect element 55 or a wiring board such as shown in
Furthermore, because the fabrication processes for the two interconnect elements or wiring boards progress simultaneously for both sides until the interconnect elements are separated from the core material 30, this can improve the manufacturing efficiency and can increase the productivity.
In this embodiment, the same structure as shown in
Following this, as shown in
Following this, as shown in
Following this, in the same manner as shown and described above relative to
When this is done, first interconnect patterns 61, overlying one major surface 63 of the interlayer insulation layer (dielectric element), protrude above the major surface 63 of the interlayer insulation layer 50, as shown in
Following this stage of fabrication, as shown in
As is shown in
Each of the aforementioned outer interconnect elements 72 and 72 includes interconnect patterns 86, which include or consist essentially of a metal such as copper which overlies an etching barrier layer 84. The etching barrier includes or consists essentially of a material such as, for example, nickel, which is not attached by an etchant which attacks the metal from which interconnect patterns 86 are made. The etching barrier layer 84, in turn, overlies a carrier layer 82, preferably including or consisting essentially of copper. A plurality of metal posts or electrically conductive pillars 88, preferably including or consisting essentially a metal such as copper extend from the interconnect patterns 86. An interlayer insulation layer 90 covers an inner surface of the interconnect patterns 86 and fills a space between the electrically conductive pillars 88. End surfaces 89 of the electrically conductive pillars 88 are exposed at an outer surface 91 of the interlayer insulation layer 90.
Furthermore, on both surfaces of the core substrate 70, interconnect elements 72 and 72 are positioned, oriented so that the end surfaces 89 of the electrically conductive pillars 88 and 88 and the outer surface 91 of the interlayer insulation layer 90 are facing the core substrate 70. The interconnect elements and the core substrate are aligned so that each of the electrically conductive pillars 88 and 88 line up with the positions of each of the outer interconnect patterns 78 and 78 of the core substrate 70.
Following this, heat and pressure are applied to join, e.g., bond, adhere or fuse the aforementioned interconnect elements 72 and 72 onto the exposed surfaces of dielectric layers and interconnect patterns 78 of the aforementioned core substrate 70.
This joining process not only strongly connects the end surfaces of each of the electrically conductive pillars 88 and 88 to the outer interconnect patterns 78 of the core substrate 70 through copper-copper bonding, but also integrates, adheres, bonds or preferably fuses the interlayer insulation layers 74 and 90 to each other.
Following this, as shown in
Following this, the aforementioned etching barrier layers 84 are removed through, for example etching, as shown in
This type of method for manufacturing can provide a multilayer interconnect element or wiring board wherein the outermost surfaces are flat and in which interconnect patterns are embedded in and are co-planar with those outermost surfaces. Such method utilizes a core substrate 70 as a base, which has indentations and protrusions on the surfaces thereof, due to the interconnection layers 78. Thereafter, the aforementioned interconnect elements 72 and 72 are aligned and joined thereto so that the electrically conductive pillars 88 and the exposed surfaces 91 of the interlayer insulation layers 90 face inward toward the core substrate 70, and so that the interconnect patterns 86 and 86 face outward.
Note that although in the embodiment described above, the number of layers for the core substrate 70 is four, and the number of layers in the multilayer interconnect element or wiring board produced therefrom is six, this is only a single example. The number of layers in the core substrate 70 is not limited to four, but rather may be a different number of layers, enabling the provision of a multilayer wiring board having a number of layers that is two layers more than the number of layers in the core substrate 70.
First, the method for manufacturing the interconnect elements 111 will be explained with reference to
As is shown in
Following this, as is shown in
Following this, on the exposed surfaces of the aforementioned interconnect patterns 108, as is shown in
Following this, as shown in
Following this, as is shown in
Following this, as is shown in
Following this, as is shown in
Following this, the ends of the aforementioned electrically conductive pillars 114 are polished or ground to adjust the height and to planarize them to the surface of the interlayer insulation layer 116, to complete the interconnect element 118, as shown in
Note that two of these interconnect elements 118 are prepared, and provided according to the processes shown in
The method for manufacturing to provide a multilayer interconnect element or wiring board according to the present embodiment will be explained next with reference to
First, as shown in
In this core interconnect element 120, four interconnection layers 122 are provided on the inside thereof, each separated and insulated from others of the layers 122 by interlayer insulation layers 124. Metal layers 126 and 126 are provided on the outermost surfaces.
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, a metal layer 134, including or consisting essentially of a metal such as copper, for example, is fabricated on the surface, as shown in
Following this, as is shown in
Following this, as shown in
The interconnect elements 118 and 118 are arranged so that the ends of the electrically conductively pillars 114 and the interlayer insulation layers 116 face the exposed surfaces of the interconnection layer 136 of the core interconnect element 120. The interconnect elements are aligned so that each of the electrically conductively pillars 114 are lined up with the interconnection layers 136 corresponding thereto. Thereafter, pressure and heat are applied to bond, adhere or fuse the interconnect elements 118 to the core interconnect element 120.
Following this, the carrier layers 102 and 102 (
This method of manufacturing produces a multilayer interconnect element or wiring board that has through holes for electrical connection between layers thereof and which has flat outer surfaces.
First, referring to
First the interconnect elements 182 (
This interconnect element 182 can be made through preparing a three-layer metal structure 180 (
Referring to
Following this, a plurality, or in the example as specifically shown, three interconnect elements 194 are stacked with interlayer insulation layers 202 interposed there between, after which the aforementioned interconnect elements for the outermost layers 182 are stacked at specific positions on both outside surfaces of the stack. Thereafter, heat and pressure are applied to join the interconnect elements 182 as outermost layers with the interconnect elements 194 disposed between them to join the components 202, 194, 194, 194, and 202.
Following this, the carrier layers 184 (
Following this, a plated underlayer 206, including or consisting essentially of a metal such as copper, for example is fabricated by electroless plating on the surface of the aforementioned layered unit, including the inner peripheral surface of the aforementioned through holes 204, after which a resist layer 208, which will serve as the mask layer for through hole fabrication, is deposited and patterned, e.g. by photolithography.
Following this, as shown in
Following this, the aforementioned resist layer 208 (
As is shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, as shown in
Following this, a second interconnect element 158a, structured from the aforementioned interconnect element 158, with the electrically conductive pillars 156 removed from the interconnect element 158 (or, more precisely, a structure wherein the electrically conductive pillars 156 were not fabricated) is provided.
Given this, the surface 155 of the interconnect element 158 from which the electrically conductive pillars 156 and the interconnection layer 150 extend and the surface 155 from which the interconnection layer 150 of the interconnect element 158a extends are disposed facing each other, and aligned so that each of the electrically conductive pillars 156 of interconnect element 158 contacts the corresponding interconnection layer 150 of interconnect element 158a. An interlayer insulation layer 160 is interposed between the interconnect element 158a and the interconnect element 158. In this state, heat and pressure are applied to join, e.g. bond, adhere or fuse the interconnect elements 158a and 158 together.
Following this, the carrier layers 142 and 142 of the interconnect elements 158 and 158a are removed, after which the etching barrier layers 144 and 144 are also removed. Thereafter, the aforementioned metal underlayers 146 and 146 are also removed.
This provides a multilayer interconnect element or wiring board wherein interconnection layers 150 are fabricated on both surfaces of an interlayer insulation layer 160, co-planar therewith.
The multilayer interconnect elements or wiring boards shown and described in this embodiment are similar to those described above, having a structure in which outermost surfaces of the dielectric elements are flat and interconnect patterns exposed at those surfaces are co-planar thereto.
On the other hand, with reference to
Referring to
In a preliminary stage of manufacturing shown in
Next, as shown in
Subsequently, as shown in
Next, as shown in
Subsequently, as illustrated in
Next, as shown in
Preferably, the underside of the cover film 222, i.e., the surface 225 of the film which faces the insulating layer 210, is substantially smooth, rather than rough. This makes the cover film easy to apply and to position in relation to the insulating layer 210. In such way, the cover film can be applied so that its position is not misaligned with the projecting conductive film 220 or an escape hole 224 that opens for it.
In addition, since the inner surface 225 of the cover film is not rough, it is easier to apply to the insulating layer and there is reduced risk that the cover film will contact a corner of the wiring film 208 and be damaged in the process, causing its protective effect to be reduced.
The wiring substrate 201 in accordance with
As further illustrated in
The packaged chip includes the chip 246 as mounted to a package substrate 242, shown here in exemplary fashion as a dielectric element 248 having conductive wiring patterns 244 on one face, that face being the side to which the chip 246 is mounted.
As particularly shown in
Other embedded wiring patterns in the substrate 230 which are in contact with the ACF 246 but not in contact with the projecting conductive film 220 are not at risk for producing unwanted conductive interconnections, e.g., becoming short-circuited. This is because the ACF 246 is compressed only where it overlies features such as the projecting conductive film 220 that extends above the surface 234 of the surface. In addition, by appropriately controlling the width 236 of the projecting conductive film 220, the force applied to compress the ACF 246 against wiring 244 can be spread over a selected surface area to assure both adequacy of contact pressure and adequacy of the surface area through the current-bearing interface between the two components to reduce resistance.
As these and other variations and combinations of the features set forth above can be utilized, the foregoing description of the preferred embodiment should be taken by way of illustration rather than by limitation of the invention.
Claims
1. An interconnect element, comprising:
- a dielectric element having a major surface and a plurality of recesses extending inwardly from said major surface;
- a plurality of metal interconnect patterns embedded in said plurality of recesses, said plurality of metal interconnect patterns having outer surfaces substantially co-planar with said major surface and extending in one or more directions of said major surface; and
- a projecting conductive film extending over said major surface in at least one direction parallel to a plane defined by said major surface to contact said dielectric element along at least a portion of said major surface and conductively contact an outer surface of at least one of said metal interconnect patterns.
2. The interconnect element as claimed in claim 1, further comprising an insulating cover film overlying only a portion of said major surface and at least one of said metal interconnect patterns such that said projecting conductive film is exposed by said insulating cover film.
3. The interconnect element as claimed in claim 1, wherein at least a portion of said projecting conductive film conductively interconnects respective ones of said metal interconnect patterns.
4. The interconnect element as claimed in claim 1, wherein said major surface is a first major surface, said dielectric element includes a second major surface remote from said first major surface and a plurality of second recesses extending inwardly from said second major surface, said metal interconnect patterns are first metal interconnect patterns embedded in said first recesses, and said interconnect element further comprises a plurality of second metal interconnect patterns embedded in said second recesses extending in one or more directions of said second major surface and having outer surfaces substantially co-planar with said second major surface, and at least some of said first metal interconnect patterns are conductively connected to at least some of said second metal interconnect patterns.
5. The interconnect element as claimed in claim 4, wherein said at least some first metal interconnect patterns are conductively connected to said at least some second metal interconnect patterns by one or more conductors extending through said dielectric element in a direction transverse to said plane defined by said first major surface of said dielectric element.
6. The interconnect element as claimed in claim 5, wherein said one or more conductors extending through said dielectric element includes a conductor lining a through hole extending through said dielectric element.
7. An assembly including the interconnect element as claimed in claim 6, further comprising an external circuit element having an exposed lead inserted into said through hole in conductive contact with said conductor to provide conductive interconnection to said interconnect element.
8. The interconnect element as claimed in claim 5, wherein said one or more conductors extending through said dielectric element includes a solid conductive post contacting inner surfaces of at least some of said first and second metal interconnect patterns recessed inwardly from said first and second major surfaces.
9. The interconnect element as claimed in claim 4, further comprising a first insulating cover film overlying a first portion of said first major surface and at least one of said first metal interconnect patterns such that said projecting conductive film is exposed by said insulating cover film.
10. An assembly including the interconnect element as claimed in claim 1, further comprising an external circuit element including an exposed contact, said contact being conductively connected to said projecting conductive film.
11. The assembly as claimed in claim 10, wherein said projecting conductive film is conductively connected to said contact through an anisotropic conductive film.
12. A method of fabricating an interconnect element, comprising:
- providing structure including a first metal layer overlying a second metal layer;
- patterning a plurality of metal interconnect patterns from said first metal layer;
- forming a dielectric element overlying said structure;
- removing said second metal layer selectively to said plurality of metal interconnect patterns, such that said plurality of metal interconnect patterns are embedded in said dielectric element, said metal interconnect patterns having outer surfaces co-planar with a first major surface of said dielectric element; and
- forming a projecting conductive film extending over said first major surface in at least one direction parallel to a plane defined by said major surface to contact said dielectric element along at least a portion of said first major surface and conductively contact an outer surface of at least one of said metal interconnect patterns.
13. The method as claimed in claim 12, wherein said step of forming said dielectric element includes pressing a layer including an uncured resin over said plurality of metal interconnect patterns.
14. The method as claimed in claim 12, wherein said metal interconnect patterns are first metal interconnect patterns embedded in first recesses extending inwardly from said first major surface, said method further comprising providing a second structure including a third metal layer overlying a fourth metal layer and patterning a plurality of second metal interconnect patterns from said third metal layer, said step of forming said dielectric element including pressing said second structure onto a second major surface of said dielectric element remote from said first major surface and removing said fourth metal layer selectively to said plurality of second metal interconnect patterns, such that said second metal interconnect patterns are embedded in said second major surface of said dielectric element and said second metal interconnect patterns have outer surfaces co-planar with said second major surface, said method further comprising:
- forming a through hole extending through said dielectric element between said first metal interconnect patterns and said second metal interconnect patterns; and
- forming a conductor lining said through hole to connect said first metal interconnect patterns to said second metal interconnect patterns simultaneously when forming said projecting conductive film.
Type: Application
Filed: May 23, 2007
Publication Date: Jun 12, 2008
Applicant: Tessera Interconnect Materials, Inc. (San Jose, CA)
Inventors: Hideki Kotake (Tokyo), Kiyoshi Hyodo (Tokyo), Inetaro Kurosawa (Tokyo), Yukio Hashimoto (Tokyo), Toku Yoshino (Tokyo), Tomoo Iijima (Tokyo)
Application Number: 11/805,300
International Classification: H01L 23/48 (20060101); H01L 21/4763 (20060101);