Patents by Inventor Yukiteru Matsui

Yukiteru Matsui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9196501
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 9174322
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming a polish target film on a substrate and conducting a CMP process for the polish target film. The conducting the CMP process includes bringing a surface of the polish target film into contact with a surface of a polishing pad with a negative Rsk value, and adjusting friction dependency on polishing speed between the polish target film and the polishing pad to a value that restrains the occurrence of a stick slip to polish the polish target film.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: November 3, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Akifumi Gawase, Hajime Eda
  • Publication number: 20150290765
    Abstract: In a substrate processing method according to an embodiment, a surface of an object to be polished disposed on a substrate is polished on a polishing pad supplied with slurry. After the polishing process using the slurry, the surface of the object to be polished on the polishing pad is polished, while supplying water on the polishing pad where a residue including the slurry or a sludge of the polishing pad adhered. After the polishing process using the water, the surface of the object to be polished is cleaned on the polishing pad by supplying rinse liquid on the polishing pad.
    Type: Application
    Filed: March 11, 2015
    Publication date: October 15, 2015
    Inventors: Yosuke OTSUKA, Masako KODERA, Yukiteru MATSUI
  • Patent number: 9144879
    Abstract: According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: September 29, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akifumi Gawase, Yukiteru Matsui, Gaku Minamihaba, Hajime Eda
  • Patent number: 9012246
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a wiring groove on an insulating film; forming a barrier metal layer and a metal layer; polishing the metal layer by applying a first load on the metal layer; and subsequently polishing the metal layer while applying a second load larger than the first load on the metal layer and spraying a gas onto a polishing pad. The polishing pad is in contact with the metal layer. The barrier metal layer covers an upper surface of the insulating film and an inner surface of the wiring groove, and the metal layer fills an inside of the wiring groove and covers the barrier metal layer.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Eda, Gaku Minamihaba, Yukiteru Matsui, Akifumi Gawase
  • Patent number: 8936729
    Abstract: According to one embodiment, a planarizing method is proposed. In the planarizing method, a surface to be processed of an object to be processed including a silicon oxide film is planarized in a processing solution by bringing the surface to be processed into contact with or close proximity with the surface of a solid-state plate on which fluorine is adsorbed. The bonding energy between fluorine and the solid-state plate is lower than that between fluorine and silicon.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akifumi Gawase, Yukiteru Matsui
  • Publication number: 20150004878
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes forming a polish target film on a substrate and conducting a CMP process for the polish target film. The conducting the CMP process includes bringing a surface of the polish target film into contact with a surface of a polishing pad with a negative Rsk value, and adjusting friction dependency on polishing speed between the polish target film and the polishing pad to a value that restrains the occurrence of a stick slip to polish the polish target film.
    Type: Application
    Filed: February 28, 2014
    Publication date: January 1, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukiteru Matsui, Akifumi Gawase, Hajime Eda
  • Patent number: 8871644
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO2, planarizing the surface of the to-be-processed film, and etching the planarized surface of the to-be-processed film.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Akifumi Gawase, Gaku Minamihaba
  • Publication number: 20140287586
    Abstract: According to one embodiment, a manufacturing method of a semiconductor device comprises forming a to-be-processed film includes a convex potion and concave potion on its surface on a semiconductor substrate via layers having a relative dielectric constant smaller than that of SiO2, planarizing the surface of the to-be-processed film, and etching the planarized surface of the to-be-processed film.
    Type: Application
    Filed: September 3, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yukiteru MATSUI, Akifumi GAWASE, Gaku MINAMIHARA
  • Publication number: 20140220778
    Abstract: According to one embodiment, a planarization method and a planarization apparatus are provided. In the planarization method, a work surface of a work piece is planarized by bringing the work surface of the work piece containing a silicon oxide film and a surface of a solid plate onto which hydrogen ions are adsorbed, into contact or extremely close proximity with one another in a state in which a process liquid containing fluorine ions is supplied to the surface of the solid plate.
    Type: Application
    Filed: September 9, 2013
    Publication date: August 7, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akifumi GAWASE, Yukiteru Matsui, Gaku Minamihaba, Hajime Eda
  • Publication number: 20140187042
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Application
    Filed: March 6, 2014
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Patent number: 8754433
    Abstract: According to one embodiment, a semiconductor device includes a switch element provided in a surface area of a semiconductor substrate, a contact plug with an upper surface and a lower surface, and a function element provided on the upper surface of the contact plug. The lower surface of the contact plug is connected to the switch element. The upper surface of the contact plug has a maximum roughness of 0.2 nm or less.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: June 17, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Hajime Eda, Masayoshi Iwayama, Minoru Amano, Masatoshi Yoshikawa, Motoyuki Sato, Kyoichi Suguro, Masako Kodera
  • Patent number: 8740667
    Abstract: According to one embodiment, a polishing method comprises pressing a substrate being rotated against a polishing pad being rotated and supplying slurry on the polishing pad, measuring a surface temperature of the polishing pad, and when the surface temperature is not less than a predetermined temperature, jetting jet stream containing supercooled droplets from a nozzle having a narrow portion toward the polishing pad.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 8703004
    Abstract: According to one embodiment, a method is disclosed for chemical planarization. The method can include forming a surface layer on a to-be-processed film having irregularity. The surface layer binds to or adsorbs onto the to-be-processed film along the irregularity to suppress dissolution of the to-be-processed film. The method can include planarizing the to-be-processed film in a processing solution dissolving the to-be-processed film, by rotating the to-be-processed film and a processing body while the to-be-processed film contacting the processing body via the surface layer, removing the surface layer on convex portions of the irregularity while leaving the surface layer on concave portions of the irregularity and making dissolution degree of the convex portions larger than dissolution degree of the concave portions.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Masako Kodera, Hiroshi Tomita, Gaku Minamihaba, Akifumi Gawase
  • Patent number: 8685857
    Abstract: There is disclosed a chemical mechanical polishing method of an organic film comprising forming the organic film above a semiconductor substrate, contacting the organic film formed above the semiconductor substrate with a polishing pad attached to a turntable, and dropping a slurry onto the polishing pad to polish the organic film, the slurry being selected from the group consisting of a first slurry and a second slurry, the first slurry comprising a resin particle having a functional group selected from the group consisting of an anionic functional group, a cationic functional group, an amphoteric functional group and a nonionic functional group, and having a primary particle diameter ranging from 0.05 to 5 ?m, the first slurry having a pH ranging from 2 to 8, and the second slurry comprising a resin particle having a primary particle diameter ranging from 0.05 to 5 ?m, and a surfactant having a hydrophilic moiety.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukiteru Matsui, Gaku Minamihaba, Yoshikuni Tateyama, Hiroyuki Yano, Atsushi Shigeta
  • Publication number: 20140073136
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises forming an interlayer dielectric film on a semiconductor substrate, forming a film on the interlayer dielectric film to cover a recess and projection formed on a surface of the interlayer dielectric film, polishing the film by CMP to expose the interlayer dielectric film, and etching the film and the interlayer dielectric film such that etching rates of the film and the interlayer dielectric film are equal.
    Type: Application
    Filed: September 3, 2013
    Publication date: March 13, 2014
    Inventors: Gaku MINAMIHABA, Akifumi Gawase, Yukiteru Matsui
  • Publication number: 20140004628
    Abstract: According to an embodiment, a method of manufacturing a semiconductor device includes forming a wiring groove on an insulating film; forming a barrier metal layer and a metal layer; polishing the metal layer by applying a first load on the metal layer; and subsequently polishing the metal layer while applying a second load larger than the first load on the metal layer and spraying a gas onto a polishing pad. The polishing pad is in contact with the metal layer. The barrier metal layer covers an upper surface of the insulating film and an inner surface of the wiring groove, and the metal layer fills an inside of the wiring groove and covers the barrier metal layer.
    Type: Application
    Filed: February 27, 2013
    Publication date: January 2, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hajime EDA, Gaku Minamihaba, Yukiteru Matsui, Akifumi Gawase
  • Publication number: 20140004775
    Abstract: According to an embodiment, a method for manufacturing a semiconductor device includes polishing a metal layer provided on a surface of a wafer, while supplying slurry to a polishing pad and spraying gas to the polishing pad. The slurry includes an inorganic particle, a resin particle, an oxidant for oxidizing the metal layer, a complexing agent for forming an organic complex on a surface of the metal layer, and a surfactant for forming a hydrophilic film on a surface of the organic complex. The resin particle includes a functional group on a surface, the functional group having a same kind of polarity as that of the inorganic particle. The resin particle contains polystyrene incorporated at a concentration of 0.001% by weight or more and 0.1% by weight or less, and has an average particle diameter of 200 nm or more and 1 ?m or less.
    Type: Application
    Filed: February 28, 2013
    Publication date: January 2, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime EDA, Gaku MINAMIHABA, Yukiteru MATSUI
  • Publication number: 20130331004
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises forming a film to be polished on a semiconductor substrate, and performing a CMP method on the film to be polished. The CMP method includes polishing the film to be polished by bringing a surface of the film to be polished into contact with a surface of a polishing pad having a negative Rsk value.
    Type: Application
    Filed: June 11, 2013
    Publication date: December 12, 2013
    Inventors: Gaku MINAMIHABA, Akifumi Gawase, Hajime Eda, Yukiteru Matsui, Satoshi Kamo, Naoki Nishiguchi, Ayako Maekawa
  • Publication number: 20130331005
    Abstract: According to one embodiment, a semiconductor device manufacturing method comprises conditioning a polishing pad by pressing a dresser against a surface of the polishing pad while keeping a surface temperature of the polishing pad at 40° C. or higher, and chemically mechanically polishing a polishing target film formed on a semiconductor substrate by pressing a surface of the polishing target film against the surface of the polishing pad having a negative Rsk value.
    Type: Application
    Filed: March 14, 2013
    Publication date: December 12, 2013
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akifumi GAWASE, Gaku MINAMIHABA, Hajime EDA, Yukiteru MATSUI