Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: A semiconductor structure includes a semiconductor substrate, a transistor, a plurality of isolation structures, and a conductive feature. The transistor is over the semiconductor substrate. The isolation structures are over the semiconductor substrate. The isolation structures define a semiconductor ring of the semiconductor substrate surrounding the transistor. The conductive feature extends vertically in the semiconductor substrate and surrounds the transistor and semiconductor ring. The conductive feature has a rounded corner facing the semiconductor ring from a top view.

Abstract: A semiconductor isolation structure includes a silicon-on-insulator wafer, a first deep trench isolation structure and a second deep trench isolation structure. The silicon-on-insulator wafer includes a semiconductor substrate, a buried insulation layer disposed on the semiconductor substrate, and a semiconductor layer disposed on the buried insulation layer. The semiconductor layer has a functional region. The first deep trench isolation structure penetrates the semiconductor layer and the buried insulation layer, and surrounds the functional region. The second deep trench isolation structure penetrates semiconductor layer and the buried insulation layer, and surrounds the first deep trench isolation structure.

Abstract: Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a first isolation structure which has a first corner. The semiconductor device also includes a first well region with a first conductive type. The semiconductor device includes further includes a gate structure over the first well region and covers a portion of the first corner of the first isolation structure. In addition, the semiconductor device includes a first doped region and a second doped region disposed on two opposites of the gate structure. Each of the first doped region and the second doped region has the first conductive type. The semiconductor device also includes a first counter-doped region in the first well region with a second conductive type different from the first conductive type. The first counter-doped region covers the first corner of the first isolation structure.

Abstract: A method for forming an integrated circuit structure is provided. The method includes forming a gate dielectric layer over a semiconductor substrate; depositing a first gate electrode layer over the gate dielectric layer; etching the first gate electrode layer to form a gate electrode over the gate dielectric layer; forming a drift region in the semiconductor substrate; depositing a dielectric layer over the gate dielectric layer and the gate electrode, in which the dielectric layer has a first portion alongside a first sidewall of the gate electrode; depositing a second gate electrode layer over the dielectric layer; etching the second gate electrode layer to form a field plate electrode alongside the first portion of the dielectric layer; and forming source/drain features in the semiconductor substrate.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A method for forming a semiconductor is provided. The method includes etching a trench in a semiconductor substrate, in which the trench surrounds a device region of the semiconductor substrate; forming a conductive feature in the trench; and forming a transistor on the device region of the semiconductor substrate after forming the conductive feature.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a source region and a drain region arranged over and/or within a substrate. Further, a shallow trench isolation (STI) structure is arranged within the substrate and between the source and drain regions. A gate electrode is arranged over the substrate, over the STI structure, and between the source and drain regions. A portion of the gate electrode extends into the STI structure such that a bottommost surface of the portion of the gate electrode is arranged between a topmost surface of the STI structure and a bottommost surface of the STI structure.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.

Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.

Abstract: A semiconductor arrangement includes a first dielectric feature passing through a semiconductive layer and a first dielectric layer over a substrate. The semiconductor arrangement includes a conductive feature passing through the semiconductive layer and the first dielectric layer and electrically coupled to the substrate. The conductive feature is adjacent the first dielectric feature and electrically isolated from the semiconductive layer by the first dielectric feature.

Abstract: A memory device includes a semiconductor substrate, a logic transistor, and a storage transistor. The semiconductor substrate has a logic region and a memory region. The logic transistor is disposed on the logic region, in which the logic transistor comprises a high-k metal gate structure. The storage transistor is disposed on the memory region, in which the storage transistor includes a charge storage structure and a high-k metal gate structure. The charge storage structure is disposed on the memory region. The high-k metal gate structure is disposed on the charge storage structure.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.