Patents by Inventor Yun-Chi Wu
Yun-Chi Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20200083233Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: ApplicationFiled: November 14, 2019Publication date: March 12, 2020Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Publication number: 20200035695Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: ApplicationFiled: September 27, 2019Publication date: January 30, 2020Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20200006365Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: ApplicationFiled: September 4, 2019Publication date: January 2, 2020Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20190393230Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: ApplicationFiled: September 6, 2019Publication date: December 26, 2019Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 10510767Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: GrantFiled: September 6, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 10510765Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.Type: GrantFiled: July 18, 2017Date of Patent: December 17, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yun-Chi Wu, Chung-Jen Huang
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Patent number: 10504912Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: GrantFiled: February 26, 2018Date of Patent: December 10, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20190140108Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: ApplicationFiled: November 27, 2018Publication date: May 9, 2019Inventors: Cheng-Bo SHU, Yun-Chi WU, Chung-Jen HUANG
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Patent number: 10276728Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: GrantFiled: July 7, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Cheng-Bo Shu, Yun-Chi Wu, Chung-Jen Huang
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Patent number: 10269822Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.Type: GrantFiled: November 30, 2016Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20190109145Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.Type: ApplicationFiled: November 21, 2018Publication date: April 11, 2019Inventors: Yun-Chi WU, Yu-Wen TSENG
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Publication number: 20190067302Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a memory cell with a large operation window and a high erase speed. In some embodiments, the IC comprises a semiconductor substrate and a memory cell. The memory cell comprises a control gate electrode, a select gate electrode, a charge trapping layer, and a common source/drain region. The common source/drain is defined by the semiconductor substrate and is n-type. The control gate electrode and the select gate electrode overlie the semiconductor substrate and are respectively on opposite sides of the common source/drain. Further, the control gate electrode overlies the charge trapping layer and comprises a metal with a p-type work function. In some embodiments, the select gate electrode comprises a metal with an n-type work function.Type: ApplicationFiled: March 26, 2018Publication date: February 28, 2019Inventors: Yun-Chi Wu, Cheng-Bo Shu, Chien Hung Liu
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Patent number: 10211217Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.Type: GrantFiled: June 20, 2017Date of Patent: February 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yun-Chi Wu, Yu-Wen Tseng
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Publication number: 20190043878Abstract: The present disclosure relates to a method of forming an embedded flash memory cell that provides for improved performance by providing for a tunnel dielectric layer having a relatively uniform thickness, and an associated apparatus. The method is performed by forming a charge trapping dielectric structure over a logic region, a control gate region, and a select gate region within a substrate. A first charge trapping dielectric etching process is performed to form an opening in the charge trapping dielectric structure over the logic region, and a thermal gate dielectric layer is formed within the opening. A second charge trapping dielectric etching process is performed to remove the charge trapping dielectric structure over the select gate region. Gate electrodes are formed over the thermal gate dielectric layer and the charge trapping dielectric structure remaining after the second charge trapping dielectric etching process.Type: ApplicationFiled: September 27, 2018Publication date: February 7, 2019Inventors: Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu, Yueh-Chieh Chu
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Publication number: 20190035799Abstract: Various embodiments of the present application are directed towards a method to integrate NVM devices with a logic or BCD device. In some embodiments, an isolation structure is formed in a semiconductor substrate. The isolation structure demarcates a memory region of the semiconductor substrate, and further demarcates a peripheral region of the semiconductor substrate. The peripheral region may, for example, correspond to BCD device or a logic device. A doped well is formed in the peripheral region. A dielectric seal layer is formed covering the memory and peripheral regions, and further covering the doped well. The dielectric seal layer is removed from the memory region, but not the peripheral region. A memory cell structure is formed on the memory region using a thermal oxidation process. The dielectric seal layer is removed from the peripheral region, and a peripheral device structure including a gate electrode is formed on the peripheral region.Type: ApplicationFiled: February 26, 2018Publication date: January 31, 2019Inventors: Cheng-Bo Shu, Chung-Jen Huang, Yun-Chi Wu
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Publication number: 20190027486Abstract: A memory device and a method for fabricating the same are provided. The memory device includes a semiconductor substrate, well regions, logic transistors, a high-voltage transistor, and a storage transistor. The well regions are disposed in the semiconductor substrate and include logic well regions, a high-voltage well region, and a memory well region. The logic transistors are disposed on the logic well regions. Each the logic transistors includes a high-k metal gate structure. The storage transistor is disposed on the memory well region, and includes a charge storage structure and a high-k metal gate structure. In the method for fabricating the memory device, a high-k first process or high-k last process is used for the formation of the high-k metal gate structures of the memory device. Because all the logic transistors and the storage transistor are formed with the high-k metal gate structure, a number of masks is decreased.Type: ApplicationFiled: July 18, 2017Publication date: January 24, 2019Inventors: Yun-Chi WU, Chung-Jen HUANG
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Publication number: 20190013414Abstract: A semiconductor device includes a non-volatile memory (NVM) cell. The NVM cell includes a semiconductor wire disposed over an insulating layer disposed on a substrate. The NVM cell includes a select transistor and a control transistor. The select transistor includes a gate dielectric layer disposed around the semiconductor wire and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the semiconductor wire and a control gate electrode disposed on the stacked dielectric layer. The stacked dielectric layer includes a charge trapping layer. The select gate electrode is disposed adjacent to the control gate electrode with the stacked dielectric layer interposed therebetween.Type: ApplicationFiled: July 7, 2017Publication date: January 10, 2019Inventors: Cheng-Bo SHU, Yun-Chi Wu, Chung-Jen HUANG
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Publication number: 20180366472Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.Type: ApplicationFiled: June 20, 2017Publication date: December 20, 2018Inventors: Yun-Chi WU, Yu-Wen TSENG
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Patent number: 10128259Abstract: A method for manufacturing embedded memory using high-?-metal-gate (HKMG) technology is provided. A gate stack is formed on a semiconductor substrate. The gate stack comprises a charge storage film and a control gate overlying the charge storage film. The control gate includes a first material. A gate layer is formed of the first material, and is formed covering the semiconductor substrate and the gate stack. The gate layer is recessed to below a top surface of the gate stack, and subsequently patterned to form a select gate bordering the control gate and to form a logic gate spaced from the select and control gates. An ILD layer is formed between the control, select, and logic gates, and with a top surface that is even with top surfaces of the control, select, and logic gates. The control, select, or logic gate is replaced with a new gate of a second material.Type: GrantFiled: July 17, 2017Date of Patent: November 13, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tsung-Yu Yang, Chung-Jen Huang, Yun-Chi Wu
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Patent number: 9799755Abstract: A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches, treating at least one portion of the insulation material, removing an upper portion of the insulation material from the trenches, so as to expose upper portions of side surfaces of the active region and to convert remaining portions of the insulation material in the trenches to shallow trench isolation (STI) disposed on opposite sides of the active region, forming a lower oxide layer, a middle charge trapping layer, and an upper oxide layer which cover the exposed upper portions of the side surfaces of the active region, an upper surface of the active region between the side surfaces of the active region, and the STI, and forming a gate layer on the upper oxide layer.Type: GrantFiled: September 14, 2016Date of Patent: October 24, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Yang, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Jui-Yu Pan, Yun-Chi Wu, Yueh-Chieh Chu