Patents by Inventor Yun Yang

Yun Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953654
    Abstract: An image capturing lens system includes, in order from an object side to an image side, a first lens element with positive refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof, a second lens element with negative refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, a third lens element with positive refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, and a fourth lens element with negative refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 9, 2024
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Chun-Che Hsueh, Hsin-Hsuan Huang, Shu-Yun Yang
  • Publication number: 20240114125
    Abstract: According to one aspect, a method includes obtaining a sensor assembly that includes at least a first camera and a second camera, and positioning the sensor assembly in an enclosure of a sensor testing system. The enclosure has a first enclosure target and a second enclosure target affixed thereon, and includes a sensor arrangement. The sensor testing assembly further includes a computing arrangement and a data acquisition arrangement, The method also includes performing a first test on the sensor assembly by providing commands to the sensor assembly using the computing arrangement, and monitoring the sensor assembly during the first test. Monitoring the sensor assembly includes obtaining data from the sensor assembly and/or the sensor arrangement, and providing the data to the data acquisition arrangement. Finally, the method includes processing the data, wherein processing the data includes determining whether the data indicates that the sensor assembly passes the first test.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 4, 2024
    Applicant: Nuro, Inc.
    Inventors: Fan Yang, Samuel Cheng, Yun Zhang, Brian Hufnagel, Tarik Snyder, Jordan Aaron, Biyu Ye
  • Publication number: 20240108817
    Abstract: An implantable microneedle and a manufacturing method therefor is disclosed. The implantable microneedle includes a coating layer for covering at least one part of the surface of a tip part of the microneedle. When exposed to moisture, the coating layer can be separated from the tip part of the microneedle and thus be implanted.
    Type: Application
    Filed: December 5, 2023
    Publication date: April 4, 2024
    Inventors: Seung Yun YANG, Sang-Gu YIM, Young Jun HWANG
  • Patent number: 11945658
    Abstract: A platform for processing a workpiece includes a transmission mechanism, a plurality of workstations and a plurality of movable vehicles. The transmission mechanism transports the workpiece to be processed to one of the plurality of workstations. Each movable vehicle includes a processing module and a docking interface adapted to connect with a docking station of each workstation. The movable vehicles are each adapted to move in and out of each workstation, and each processing module is adapted to process the workpiece transmitted to the workstation after the movable vehicle is moved in and positioned in the workstation.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: April 2, 2024
    Assignees: TE Connectivity Solutions GmbH, Tyco Electronics (Shanghai) Co., Ltd., Tyco Electronics (Qingdao) Ltd.
    Inventors: Jian Cao, Lvhai (Samuel) Hu, Dandan (Emily) Zhang, Fengchun (Fred) Xie, An (Joshua) Yang, Yun (Shanghai) Liu, Wenhe Ma, Peng Ji, Zongjie (Jason) Tao, Roberto Francisco-Yi Lu, Tao Xu
  • Patent number: 11949961
    Abstract: A computer-implemented method for optimizing the placement of previously selected breaks in a media item is provided herein. Embodiments of the method include steps of identifying a break in a media item, the break being associated with a first break point at a first time during playback of the media item. The method may also include steps of dynamically adjusting the placement of the breaks within the media item based on the performance of the media item.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 2, 2024
    Assignee: GOOGLE LLC
    Inventors: Yun Shi, Jianfeng Yang, Ramesh Sarukkai, Zindziswa Lara McCormick
  • Patent number: 11947744
    Abstract: The present disclosure relates to a device for providing augmented reality that can accurately recognize a writing tool such as an electronic pen to realize motion information of the writing tool over augmented reality contents, and a method for providing augmented reality using the same. According to some embodiments of the disclosure, an augmented reality device includes at least one transparent lens, a support frame supporting the at least one transparent lens, at least one display module configured to display augmented reality contents through the at least one transparent lens, a sensing module at a front of the support frame, and configured to generate image data, and a control module configured to receive motion-sensing signals of an electronic pen to detect motion information of the electronic pen, and configured to modulate the augmented reality contents so that the motion information of the electronic pen is includes therein.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 2, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Hee Lee, Byung Choon Yang, Joo Woan Cho, Byeong Hwa Choi, Hae Yun Choi
  • Patent number: 11949591
    Abstract: The present disclosure provides a method (100) in a network node advertising a Binding Segment Identifier, BSID. The method (100) includes: receiving (110) a first echo request packet containing a first target Forwarding Equivalence Class, FEC, stack including an FEC associated with the BSID; and transmitting (120), in response to a Time To Live, TTL, expiration associated with the first echo request packet, a first echo reply packet to an initiating network node initiating the first echo request packet, the first echo reply packet containing an indicator indicating that the FEC is to be replaced by a set of FECs.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: April 2, 2024
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Ying Lu, Shuo Yang, Wei Sun, Jinfeng Zhao, Yun Lin
  • Patent number: 11938308
    Abstract: The present invention provides an implantable microneedle and a manufacturing method therefor. An implantable microneedle according to the present invention comprises a coating layer for covering at least one part of the surface of a tip part of the microneedle. When exposed to moisture, the coating layer can be separated from the tip part of the microneedle and thus be implanted.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: March 26, 2024
    Assignee: SNVIA CO., LTD.
    Inventors: Seung Yun Yang, Sang-Gu Yim, Young Jun Hwang
  • Patent number: 11942485
    Abstract: A substrate includes a driving backplane, a plurality of first connecting lines and a plurality of second connecting lines. The driving backplane includes a base substrate, at least one first lead group and at least one second lead group. Each first lead group includes a plurality of first leads, and each second lead group includes a plurality of second leads. A first lead group and a corresponding second lead group is disposed in a peripheral region. The plurality of first connecting lines are disposed on at least one side face of the driving backplane, each first connecting line is electrically connected to at least one first lead. The plurality of second connecting lines are disposed on the at least one side face of the driving backplane, each second connecting line is electrically connected to at least one second lead, and is in contact with a corresponding first connecting line.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: March 26, 2024
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yonglian Qi, Hong Yang, Lianjie Qu, Shan Zhang, Hebin Zhao, Yun Qiu
  • Publication number: 20240092817
    Abstract: Embodiments of the present application relate to polymers used as polymeric polyvalent hub for liquid phase oligonucleotide synthesis. Methods for making an oligonucleotide by liquid phase oligonucleotide synthesis using the polyvalent hub are also provided.
    Type: Application
    Filed: November 9, 2023
    Publication date: March 21, 2024
    Inventors: Gaomai Yang, Yun-Chiao Yao, David Yu, Aldrich N.K. Lau
  • Publication number: 20240098960
    Abstract: An integrated circuit structure in which a gate overlies channel region in an active area of a first transistor. The first transistor includes a channel region, a source region and a drain region. A conductive contact is coupled to the drain region of the first transistor. A second transistor that includes a channel region, a source region a drain region is adjacent to the first transistor. The gate of the second transistor is spaced from the gate of the first transistor. A conductive via passes through an insulation layer to electrically connect to the gate of the second transistor. An expanded conductive via overlays both the conductive contact and the conductive via to electrically connect the drain of the first transistor to the gate of the second transistor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 21, 2024
    Inventors: YU-KUAN LIN, CHANG-TA YANG, PING-WEI WANG, KUO-YI CHAO, MEI-YUN WANG
  • Publication number: 20240097035
    Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chen-Ming Lee, I-Wen Wu, Po-Yu Huang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240096985
    Abstract: Methods and devices including an air gap adjacent a contact element extending to a source/drain feature of a device are described. Some embodiments of the method include depositing a dummy layer, which is subsequently removed to form the air gap. The dummy layer and subsequent air gap may be formed after a SAC dielectric layer such as silicon nitride is formed over an adjacent metal gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: I-Wen WU, Chen-Ming LEE, Fu-Kai YANG, Mei-Yun WANG
  • Publication number: 20240091366
    Abstract: The present invention relates to the field of pharmaceutical and chemical engineering, and specifically relates to a weakly acidic microenvironment-sensitive aptamer for tumors, a triptolide conjugate. The conjugate is formed by conjugation between the 14-position hydroxyl group of triptolide and the aptamer via an acetal ester linking bond, which is an acid-sensitive linking bond with a cleavage condition of (pH=3.5-6.5), which is much less pH-sensitive and is more likely to cleave under the tumor microenvironment. Based on the characteristics of the aptamer targeting the highly expressed proteins on the membrane surface of tumor cells, the conjugate delivered triptolide targeted to tumor cells and mediated endocytosis to reach the lysosome; based on the characteristics of the acidic environment of lysosomes, the acetal ester linking bond released intact triptolide in the lysosomal acidic environment, targeting and killing of tumor cells.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 21, 2024
    Inventors: Jun LU, Yun DENG, Yao CHEN, Jirui YANG, Yi ZUO, Xiao LI, Qing REN
  • Publication number: 20240096999
    Abstract: A device includes a gate stack; a gate spacer on a sidewall of the gate stack; a source/drain region adjacent the gate stack; a silicide; and a source/drain contact electrically connected to the source/drain region through the silicide. The silicide includes a conformal first portion in the source/drain region, the conformal first portion comprising a metal and silicon; and a conformal second portion over the conformal first portion, the conformal second portion further disposed on a sidewall of the gate spacer, the conformal second portion comprising the metal, silicon, and nitrogen.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Inventors: Kai-Di Tzeng, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11935932
    Abstract: In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Han Chen, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240090230
    Abstract: A memory array and an operation method of the memory array are provided. The memory array includes first and second ferroelectric memory devices formed along a gate electrode, a channel layer and a ferroelectric layer between the gate electrode and the channel layer. The ferroelectric memory devices include: a common source/drain electrode and two respective source/drain electrodes, separately in contact with a side of the channel layer opposite to the ferroelectric layer, wherein the common source/drain electrode is disposed between the respective source/drain electrodes; and first and second auxiliary gates, capacitively coupled to the channel layer, wherein the first auxiliary gate is located between the common source/drain electrode and one of the respective source/drain electrodes, and the second auxiliary gate is located between the common source/drain electrode and the other respective source/drain electrode.
    Type: Application
    Filed: January 9, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Ling Lu, Chen-Jun Wu, Ya-Yun Cheng, Sheng-Chih Lai, Yi-Ching Liu, Yu-Ming Lin, Feng-Cheng Yang, Chung-Te Lin
  • Patent number: 11930672
    Abstract: A display device includes a substrate including a display area and a non-display area, the display area including pixels; data lines extending into the display area and connected to pixels; a first input pad in the non-display area and connected to the data lines; a switching transistor located in the non-display area between the first input pad and one side of the substrate and connected to the first input pad; and a second input pad in the non-display area and connected to a gate electrode of the switching transistor through a switching line.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: March 12, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventor: Yeong-Yun Yang
  • Patent number: 11930624
    Abstract: An electronic device protecting casing with heating function includes: a casing; a battery box within the casing; an interior of the battery box being arranged with a battery, a back side of the battery box being formed with an opening for receiving the battery; an outer cover serving to seal the opening; an inner side of the outer cover being formed with a heat isolation sheet; a heating unit being installed within the casing for heating the tablet computer; the heating unit including an electric heating plate. When power of the battery is transferred to the electric heating plate, the electric heating plate generates heat power and then transfers the power to the tablet computer for heating it; and a control circuit is installed within the casing; the electric heating plate is connected to the battery through a control switch; and the control circuit is connected to the control switch.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: March 12, 2024
    Assignee: THE JOY FACTORY, INC.
    Inventors: Sampson Yang, Yun-Chang Tsui, Jui-Lin Wu
  • Patent number: 11927631
    Abstract: Provided test method and apparatus of communication chip, device and medium. The test method of communication chip includes receiving end test method and transmitting end test method. The receiving end test method of the communication chip includes: an idle time slot of the receiving end of the communication chip is detected in a running process of the communication chip; a test vector is generated, and a standard result corresponding to the test vector is generated; a data frame containing the test vector is constructed, and the data frame is sent to the receiving end of the communication chip in the idle time slot to enable the receiving end of the communication chip to process the data frame; and a chip processing result uploaded by the receiving end of the communication chip is received, and the standard result is compared with the chip processing result.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: March 12, 2024
    Assignee: MORNINGCORE TECHNOLOGY CO., CHINA
    Inventors: Shanzhi Chen, Guobin Su, Yun Yang