Abstract: A magnetic sensing device including a substrate having a supporting surface on which a first sensing area, a third sensing area, and a second sensing area are consecutively arranged in a direction of movement. The first, the second, and the third sensing areas are provided with a first midline, a second midline, and a third midline in the direction of movement, respectively. The first and second midlines are symmetrical with respect to the third midline. The first and second sensing areas are jointly configured to output a first output signal. The third sensing area is configured to output a second output signal. A phase difference between the first and second output signals is 90 degrees, and the first and second output signals are jointly configured to determine the distance or the speed or the angle of movement and the direction of movement of the relative motion.

Abstract: A method includes forming a dummy gate over a semiconductor fin; forming a source/drain epitaxial structure over the semiconductor fin and adjacent to the dummy gate; depositing an interlayer dielectric (ILD) layer to cover the source/drain epitaxial structure; replacing the dummy gate with a gate structure; forming a dielectric structure to cut the gate structure, wherein a portion of the dielectric structure is embedded in the ILD layer; recessing the portion of the dielectric structure embedded in the ILD layer; after recessing the portion of the dielectric structure, removing a portion of the ILD layer over the source/drain epitaxial structure; and forming a source/drain contact in the ILD layer and in contact with the portion of the dielectric structure.

Abstract: A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a via, a liner layer, a barrier layer, and a conductor. The via penetrates through the substrate. The liner layer is formed on a sidewall of the via. The barrier layer is formed on the liner layer. The barrier layer comprises a conductive 2D material. The conductor fills a remaining space of the via.

Abstract: A method for fabricating semiconductor devices includes forming channel regions over a substrate. The channel regions, in parallel with one another, extend along a first lateral direction. Each channel region includes at least a respective pair of epitaxial structures. The method includes forming a gate structure over the channel regions, wherein the gate structure extends along a second lateral direction. The method includes removing, through a first etching process, a portion of the gate structure that was disposed over a first one of the channel regions. The method includes removing, through a second etching process, a portion of the first channel region. The second etching process includes one silicon etching process and one silicon oxide deposition process. The method includes removing, through a third etching process controlled based on a pulse signal, a portion of the substrate that was disposed below the removed portion of the first channel region.

Abstract: Various embodiments disclose a method for operating a printer apparatus that includes a print head. The method includes causing a media hub to retract a media in a retract direction along a media path. Further, the method includes causing a first media sensor to generate a first signal during retraction of the media. Furthermore, the method includes monitoring the first signal to detect at least one of a leading edge or a trailing edge of a label of the plurality of labels. Upon detecting the at least one of the leading edge or the trailing edge of the label, causing the media hub to retract the media by at least a predetermined distance, wherein the predetermined distance is a distance between the print head and the first media sensor.

Abstract: A device includes a substrate, a chalcogenide channel layer, a chalcogenide barrier layer, source/drain contacts, and a gate electrode. The chalcogenide channel layer is over the substrate. The chalcogenide barrier layer is over the chalcogenide channel layer. A dopant concentration of the chalcogenide barrier layer is greater than a dopant concentration of the chalcogenide channel layer. The source/drain contacts are over the chalcogenide channel layer. The gate electrode is over the substrate.

Abstract: A micro light-emitting diode display panel includes a substrate, at least one light-emitting element, a reflective layer and a light-absorbing layer. The at least one light-emitting element is disposed on the substrate to define at least one pixel, and each light-emitting element includes micro light-emitting diodes. The reflective layer is disposed on the substrate and located between the micro light-emitting diodes. The reflective layer has cavities surrounding the micro light-emitting diodes, such that a thickness of a portion of the reflective layer close to any one of the micro light-emitting diodes is greater than a thickness of a portion of the reflective layer away from the corresponding micro light-emitting diode. The light-absorbing layer is at least disposed in the cavities of the reflective layer.

Abstract: The present disclosure relates to a semiconductor device with a hybrid fin-dielectric region. The semiconductor device includes a substrate, a source region and a drain region laterally separated by a hybrid fin-dielectric (HFD) region. A gate electrode is disposed above the HFD region and the HFD region includes a plurality of fins covered by a dielectric and separated from the source region and the drain region by the dielectric.

Abstract: The application provides a memory device and an operation method thereof. The memory device includes: a memory array, for processing model computation having a plurality of input values and a plurality of interact coefficients; and at least one calculation unit. In receiving the input values, a first part and a second part of the memory cells generate a first part and a second part of the common source currents, respectively. The first part of the memory cells is electrically isolated from the second part of the memory cells based on a diagonal of the memory array. The at least one calculation unit calculates a first part and a second part of a local field energy of the model computation based on the first part and the second part of the common source currents.

Abstract: A device includes a substrate, a channel layer, a barrier layer, a gate electrode, and source/drain contacts. The channel layer is made of transition metal dichalcogenide. The barrier layer is over the channel layer. The gate electrode is over the barrier layer. The source/drain contacts are on opposite sides of the gate electrode and over the barrier layer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate and a via structure. The via structure is through the substrate. The via structure includes a first conductive portion, a second conductive portion, a first barrier portion, a second barrier portion, and a third barrier portion. The first conductive portion has a ring-shaped cross section. The second conductive portion is disposed at an inner side of the first conductive portion. The second conductive portion has a ring-shaped cross section. The first barrier portion is disposed at an outer side of the first conductive portion. The second barrier portion is disposed between the first conductive portion and the second conductive portion. The third barrier portion is disposed at an inner side of the second conductive portion. At least one of the first barrier portion, the second barrier portion, or the third barrier portion includes an insulating 2D material.

Abstract: A memory device is provided. The memory device includes a memory array of a plurality of memory elements, a plurality of word lines or word line pairs, a plurality of bit line pairs, and a plurality of common source lines. Each of the memory elements includes two memory cells. The memory device is configured for calculating an energy value based on a plurality of state signals and a plurality of coefficients, and the two memory cells of each of the memory elements are configured for performing an individual selection such that one of the two memory cells of each of the memory elements receives two corresponding state signals from a corresponding word line or a corresponding word line pair and a corresponding bit line pair and generates an output current into a corresponding common source line for calculating the energy value.

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.

Abstract: A method for standardizing image annotation includes receiving a defect pattern; marking an image according to the defect pattern to generate a first judgement result; marking the image according to the defect pattern to generate a second judgement result; comparing the first judgement result and the second judgement result to obtain a comparison result; and updating the defect pattern according to the comparison result to standardize the defect pattern. The method for standardizing image annotation of the present specification can improve the marking stability of the training data of a trained image recognition algorithm, thereby improving the accuracy of image recognition of the trained image recognition algorithm.

Abstract: A method of measuring hematocrit is provided. The method for measuring hematocrit includes the following steps. A test strip is provided. The test strip includes a reaction region and a pair of electrodes disposed in the reaction region. A whole blood sample is entered to the reaction region. After the whole blood sample enters the reaction region, a plurality of sets of square wave voltages are intermittently applied to the pair of electrodes based on a square wave voltammetry method to obtain a plurality of feedbacks related to hematocrit. An interval between two adjacent sets of square wave voltages ranges from 0.1 seconds to 4 seconds. A feedback of an n-th set of square wave voltages is obtained to calculate a hematocrit value of the whole blood sample and n is a positive integer greater than 1. A hematocrit value is calculated according to the feedback.

Abstract: A memory device, for executing an anneal computation with first state and a second state. The memory device includes a first memory array, a second memory array, a control circuit, a sensing circuit and a processing circuit. the control circuit selects a first horizontal row of memory units from the first memory array, and selects a second horizontal row of memory units from the second memory array. The sensing circuit computes a local energy value of the first state according to the current generated by the memory units of the first horizontal row, and computes a local energy value of the second state according to the current generated by the memory units of the second horizontal row. The processing circuit updates the first state and/or the second state according to the local energy value of the first state and the local energy value of the second state.

Abstract: Embodiments provide for automated testing of an Application Under Test (AUT) that utilizes an infinite scroll element. Automated testing of the AUT can comprise executing one or more test scripts on the AUT which can present a user interface including a plurality of elements and the test scripts can perform one or more functional tests on the AUT through the plurality of elements of the user interface. During performance of the one or more functional tests, a scroll event associated with an element of the user interface can be detected and a determination can be made as to whether the element associated with the scroll event is an infinite scroll element. In response to determining the element is an infinite scroll element, a set of test results for the functional test can be recorded including results for the infinite scroll element and an interaction with the infinite scroll element.