Patents by Inventor Yung-Hsiang Chen

Yung-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153860
    Abstract: An electronic device is provided. The electronic device includes a redistribution structure, an electronic unit and a first conductive pad. The first conductive pad is disposed between the redistribution structure and the electronic unit. The electronic unit is electrically connected to the redistribution structure through the first conductive pad. The first conductive pad has a first coefficient of thermal expansion and a first Young's modulus. The first coefficient of thermal expansion and the first Young's modulus conform to the following formula: 0.7×(0.0069E2?1.1498E+59.661)?CTE?1.3×(0.0069E2?1.1498E+59.661), wherein CTE is the first coefficient of thermal expansion, and E is the first Young's modulus in the formula.
    Type: Application
    Filed: December 21, 2022
    Publication date: May 9, 2024
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Yung-Feng CHEN, Ming-Hsien SHIH
  • Publication number: 20240145370
    Abstract: A semiconductor device includes a first region and a second region, and the second region surrounds the first region. The semiconductor device includes at least one electronic unit, a redistribution structure, a plurality of first pads, and a plurality of second pads. The redistribution structure may be electrically connected to at least one electronic unit. A plurality of first pads are arranged on the redistribution structure and correspondingly to the first region. There is a first pitch between two adjacent first pads. A plurality of second pads are arranged on the redistribution structure and correspondingly to the second region. There is a second pitch between two adjacent second pads, so that the first pitch is smaller than the second pitch.
    Type: Application
    Filed: December 18, 2022
    Publication date: May 2, 2024
    Applicant: InnoLux Corporation
    Inventors: Te-Hsun LIN, Wen-Hsiang LIAO, Ming-Hsien SHIH, Yung-Feng CHEN, Cheng-Chi WANG
  • Publication number: 20240139261
    Abstract: Provided is a composition for improving gut microbiota, including: a bacterial species combination consisting of Limosilactobacillus fermentum TCI275 with an accession number of BCRC 910940, Bifidobacterium animalis subsp. lactis TCI604 with an accession number of BCRC 910887, and Weizmannia coagulans TCI803 with an accession number of BCRC 910946. Provided is a method for improving gut microbiota of a subject in need thereof with the bacterial species combination.
    Type: Application
    Filed: October 31, 2022
    Publication date: May 2, 2024
    Inventors: YUNG-HSIANG LIN, CHU-HAN HUANG, YI-LIN CHEN
  • Patent number: 11973148
    Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
  • Patent number: 11965898
    Abstract: An automatic nucleic acid detection system and a method thereof are disclosed. The automatic nucleic acid detection method includes: performing, by an automatic control subsystem, on a nucleic acid extraction machine platform, a nucleic acid extraction on one or more specimens in a sample tray to generate one or more corresponding nucleic acids in the sample tray; distributing, by the automatic control subsystem, on a nucleic acid distribution machine platform, the nucleic acid in each hole of the sample tray and a first reagent into a plurality of holes of a detection tray, wherein the number of holes of the detection tray is greater than that of the sample tray; and performing, by the automatic control subsystem, on a nucleic acid detection machine platform, a nucleic acid detection on the detection tray.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 23, 2024
    Assignees: TCI GENE INC, TCI CO., LTD
    Inventors: Yung-Hsiang Lin, Cheng-Hong Hsieh, Ciao-Ting Chen, Tsung-Cheng Chen
  • Publication number: 20240117837
    Abstract: A foldable electronic device includes a first body, a second body, a first hinge module, a second hinge module, a driving sheet, and a one-way bearing. The first body has a display surface and a back surface. The first hinge module has a first shaft pivotally connected to the first body and a second shaft pivotally connected to the second body. The second shaft has a virtual axis. The second hinge module is disposed to the second body and has a rotating shaft. The rotating shaft is disposed corresponding to the virtual axis. The driving sheet is located between the first shaft and the second shaft, and is located between the first hinge module and the second hinge module. The one-way bearing is rotatably disposed around the rotating shaft. The one-way bearing has a bearing stop portion corresponding to the driving sheet.
    Type: Application
    Filed: April 24, 2023
    Publication date: April 11, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Tsung-Ju Chiang, Yung-Hsiang Chen
  • Publication number: 20240094600
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly and a first driving assembly. The movable assembly is movable relative to the fixed assembly. The first driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The optical element driving mechanism further includes a first opening, and an external light beam travels along a first axis to pass through the first opening.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 21, 2024
    Inventors: Tso-Hsiang WU, Chao-Chang HU, Yung-Yun CHEN, Ya-Hsiu WU
  • Patent number: 11923295
    Abstract: A semiconductor structure includes a first dielectric layer over a first conductive line and a second conductive line, a high resistance layer over a portion of the first dielectric layer, a second dielectric layer on the high resistance layer, a low-k dielectric layer over the second dielectric layer, a first conductive via extending through the low-k dielectric layer and the second dielectric layer, and a second conductive via extending through the low-k dielectric layer and the first dielectric layer to the first conductive line. The first conductive via extends into the high resistance layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hong-Wei Chan, Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen
  • Patent number: 11901754
    Abstract: The disclosure provides a charging base. The charging base is applied to electrically connect to an electronic device and charge a stylus. The charging base includes: a base, a connector, a first charging end conductive structure, and a second charging end conductive structure. The base includes a through-hole. The connector is disposed on one side of the base and is used for being electrically connected to the electronic device. The first charging end conductive structure is formed on an upper surface of the base and is electrically connected to the connector. The second charging end conductive structure is formed in the through-hole and is electrically connected to the connector.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 13, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Chin Chung Lai, Yung-Hsiang Chen
  • Publication number: 20240045343
    Abstract: A method includes providing a workpiece to a semiconductor apparatus, the workpiece including a material layer including a first strip having: a first plurality of exposure fields; and a second plurality of exposure fields alternatingly arranged with the first plurality of exposure fields. The method further includes: scanning the first strip along a first scan route from a first side of the workpiece to a second side of the workpiece to generate first topography measurement data; scanning the first strip along a second scan route from the second side to the first side to generate second topography measurement data; and exposing the first plurality of exposure fields and exposing the second plurality of exposure fields according to the first topography measurement data and the second topography measurement data.
    Type: Application
    Filed: October 23, 2023
    Publication date: February 8, 2024
    Inventors: YUNG-YAO LEE, YEH-CHIN WANG, YANG-ANN CHU, YUNG-HSIANG CHEN, YUNG-CHENG CHEN
  • Patent number: 11892873
    Abstract: The disclosure provides a computer device. The computer device includes a base, a host case, and a display support. The base includes an upper surface and includes a power module therein. The host case is detachably fixed to the base and electrically connected to the power module through the upper surface. One end of the display support is connected to the base, and the other end thereof includes a display connection structure.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: February 6, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yung-Hsiang Chen, Li-Hsiang Chiu, Marco Da Ros, Li-Wei Hung
  • Patent number: 11892884
    Abstract: A hinge structure for an electronic device including a first part and a second part is provided. The hinge structure includes a first fixing base, a second fixing base, a rotating element, and a control element. The first fixing base connects to the first part. The second fixing base connects to the second part and includes a first locking structure. The rotating element includes a second locking structure. An end of the rotating element rotatably and movably connects to the first fixing base along an axial direction. The other end of the rotating element engages with the first locking structure through the second locking structure. The control element extends to the rotating element for driving the rotating element to move along the axial direction.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: February 6, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Tsung-Ju Chiang, Marco Da Ros, Yung-Hsiang Chen, Li Wei Hung
  • Publication number: 20240018685
    Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 18, 2024
    Inventors: Yung-Hsiang CHEN, Hung-San LU, Ting-Ying WU, Chuang CHIHCHOUS, Yu-Lung YEH
  • Patent number: 11871531
    Abstract: A computer device and a host module thereof are provided. The host module includes a case, a motherboard, and a power supply unit. The case includes a first side plate, a second side plate, a front panel, a rear panel, and a separation structure. The rear panel is located on an opposite side of the front panel. The first side plate, the second side plate, the front panel, and the rear panel enclose an internal space. The separation structure is located in the internal space, extends from the first side plate to the second side plate, and divides the internal space into a first part and a second part. The second part is located under the first part. The motherboard is disposed in the first part. The power supply unit is disposed in the second part, and is electrically connected to the motherboard.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: January 9, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yung-Hsiang Chen, Marco Da Ros, Li-Wei Hung, Li-Hsiang Chiu
  • Patent number: 11835866
    Abstract: A method includes: providing a workpiece to a semiconductor apparatus, the workpiece including a material layer, wherein the material layer includes a first strip having a first plurality of exposure fields configured to be exposed in a first direction and a second plurality of exposure fields configured to be exposed in a second direction different from the first direction; scanning the first strip along a first scan route in the first direction to generate first topography measurement data; scanning the first strip along a second scan route in the second direction to generate second topography measurement data; and exposing the first plurality of exposure fields according to the first topography measurement data and exposing the second plurality of exposure fields according to the second topography measurement data.
    Type: Grant
    Filed: October 31, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yung-Yao Lee, Yeh-Chin Wang, Yang-Ann Chu, Yung-Hsiang Chen, Yung-Cheng Chen
  • Patent number: 11814743
    Abstract: A plating membrane includes a support structure extending radially outward from a nozzle that is to direct a flow of a plating solution toward a wafer. The plating membrane also includes a frame, supported by the support structure, having an inner wall that is angled outward from the nozzle. The outward angle of the inner wall relative to the nozzle directs a flow of plating solution from the nozzle in a manner that increases uniformity of the flow of the plating solution toward the wafer, reduces the amount of plating solution that is redirected inward toward the center of the plating membrane, reduces plating material voids in trenches of the wafer (e.g., high aspect ratio trenches), and/or the like.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Hsiang Chen, Hung-San Lu, Ting-Ying Wu, Chuang Chihchous, Yu-Lung Yeh
  • Patent number: 11809227
    Abstract: An electronic device is provided. The electronic device includes a function module, a casing, and a cover. The casing includes a space to accommodate the function module. The cover includes a frame and an extending portion. The frame covers the casing. The extending portion extends outward from a sidewall of the frame to protrude from the casing, and the extending portion and the frame are integrally formed.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: November 7, 2023
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yi-Chen Yen, Yung-Hsiang Chen, Hsi-Tan Huang
  • Patent number: 11784627
    Abstract: A Lamb wave resonator includes a piezoelectric material layer, a first finger electrode, a second finger electrode, at least two floating electrodes, and at least two gaps. The first finger electrode is disposed on one side of the piezoelectric material layer and includes a first main portion and first fingers. The second finger electrode is disposed on the side of the piezoelectric material layer and includes a second main portion and second fingers. The first fingers are parallel to and alternately arranged with the second fingers. The floating electrodes are disposed between each first finger and each second finger, and the gaps are disposed at two ends of each floating electrode, respectively.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: October 10, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Yu Chang, Yen-Lin Chen, Chien-Hui Li, Tai-I Yang, Yung-Hsiang Chen
  • Publication number: 20230307268
    Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yung-Hsiang Chen, Yun-Chou Wei, Ke-Fang Hsu, Ching-Yi Hsu, Yen-Shih Ho
  • Publication number: 20230229085
    Abstract: A method and corresponding spin coater is provided for forming a layer of uniform thickness on a semiconductor wafer having a central region and an outer edge. The method includes: depositing a flowable coating material on the semiconductor wafer at the central region, the layer being formed from the coating material; rotating the semiconductor wafer about an axis such that a centrifugal force urges the coating material to spread from the central region toward the outer edge of the semiconductor wafer; and creating a pressure differential in one or more regions proximate to the outer edge of the semiconductor wafer. The pressure differential may be created by a wall with pins holes, the wall at least partially encircling the outer edge of the semiconductor wafer.
    Type: Application
    Filed: January 19, 2022
    Publication date: July 20, 2023
    Inventors: Yung-Yao Lee, Yung-Hsiang Chen