Abstract: A semiconductor device includes a metal gate stack. The metal gate stack includes a high-k gate dielectric and a metal gate electrode over the high-k gate dielectric. The metal gate electrode includes a first top surface and a second bottom surface substantially diametrically opposite the first top surface. The first top surface includes a first surface length and the second bottom surface includes a second surface length. The first surface length is larger than the second surface length. A method of forming a semiconductor device is provided.

Abstract: A method and system for pins detection and insertion of an electronic component are provided. The method includes picking an electronic component having a plurality of pins by a pick and place device, acquiring a plurality of serial images with respect to the plurality of pins at different height along an image acquiring direction by an image acquiring device, separately detecting image positions corresponding to the plurality of pins in the plurality of serial images, determining whether the electronic component is qualified according to a distance between the image positions of two adjacent pins, and if the electronic component is qualified, inserting the electronic component to a circuit board according to a position relationship between the image positions of the pins and a geometric center position of the pick and place device.

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract: The present disclosure relates to a method of forming a gate structure that can be selectively adjusted to reduce critical-dimension (CD) variations. In some embodiments, the method is performed by forming a gate structure having a first length over a semiconductor substrate. The first length of the gate structure is measured and compared to a target length. If the first length differs from the target length by an amount that is greater than a threshold value, the first length is adjusted to converge upon the target length. By selectively adjusting the length of the gate structure, critical-dimension (CD) variations can be reduced, thereby increasing yield and reducing cost.

Abstract: A semiconductor device having arrays of metal gate transistors is fabricated by forming a number of dummy gate structures including a first gate dielectric layer and a dummy gate material layer overlying the first gate dielectric layer, depositing a tensile ILD layer between the dummy gate structures, stressing the tensile ILD layer, removing at least the dummy gate material to form a number of trenches, and depositing a metal gate material in the trenches, which have a tapered profile.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and a fin structure extending above the substrate. The FinFET structure includes an epitaxial structure formed on the fin structure, and the epitaxial structure has a first height. The FinFET structure also includes fin sidewall spacers formed adjacent to the epitaxial structure. The sidewall spacers have a second height and the first height is greater than the second height, and the fin sidewall spacers are configured to control a volume and the first height of the epitaxial structure.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.

Abstract: A semiconductor device and method of forming the same are disclosed. The method includes receiving a substrate having an active fin, an oxide layer over the active fin, a dummy gate stack over the oxide layer, and a spacer feature over the oxide layer and on sidewalls of the dummy gate stack. The method further includes removing the dummy gate stack, resulting in a first trench; etching the oxide layer in the first trench, resulting in a cavity underneath the spacer feature; depositing a dielectric material in the first trench and in the cavity; and etching in the first trench so as to expose the active fin, leaving a first portion of the dielectric material in the cavity.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device structure also includes a sealing structure over a sidewall of the gate stack , and a width ratio of the sealing structure to the gate stack is in a range from about 0.05 to about 0.7. The semiconductor device structure further includes an etch stop layer over the semiconductor substrate, the gate stack, and the sealing structure . The etch stop layer is in contact with the sealing structure.

Abstract: A device may include: a high-k layer disposed on a substrate and over a channel region in the substrate. The high-k layer may include a high-k dielectric material having one or more impurities therein, and the one or more impurities may include at least one of C, Cl, or N. The one or more impurities may have a molecular concentration of less than about 50%. The device may further include a cap layer over the high-k layer over the channel region, the high-k layer separating the cap layer and the substrate.

Abstract: Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: Embodiments of a method for forming a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate and forming a sealing structure over a sidewall of the gate stack. The method also includes forming a dummy shielding layer over the semiconductor substrate, the sealing structure, and the gate stack. The method further includes performing an ion implantation process on the dummy shielding layer to form source and drain regions in the semiconductor substrate. In addition, the method includes removing the dummy shielding layer after the source and drain regions are formed.

Abstract: Disclosed herein is a method forming a device comprising forming a high-k layer over a substrate and applying a dry plasma treatment to the high-k layer and removing at least a portion of one or more impurity types from the high-k layer. The dry plasma treatment may be chlorine, fluorine or oxygen plasma treatment. A cap layer may be applied on the high-k layer and a metal gate formed on the cap layer. An interfacial layer may optionally be formed on the substrate, with the high-k layer is formed on the interfacial layer. The high-k layer may have a dielectric constant greater than 3.9, and the cap layer may optionally be titanium nitride. The plasma treatment may be applied after the high-k layer is applied and before the cap layer is applied or after the cap layer is applied.

Abstract: Embodiments of mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a substrate and a first fin structure extending above the substrate. The FinFET also includes a first transistor formed on the first fin structure. The first transistor includes a first gate dielectric layer conformally formed on the first fin structure and a first gate electrode formed on the first gate dielectric layer. The FinFET further includes an inter-layer dielectric (ILD) structure formed adjacent to the first transistor. The first gate electrode is in direct contact with a sidewall of the ILD structure.

Abstract: In some embodiments, an field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: Embodiments for forming a fin field effect transistor (FinFET) device structure are provided. The FinFET device structure includes a fin structure extending above a substrate and a gate dielectric layer formed over the fin structure. The FinFET device structure also includes a gate electrode formed on the gate dielectric layer. The FinFET device structure further includes a number of gate spacers formed on sidewalls of the gate electrode. The gate spacers are in direct contact with the fin structure.

Abstract: In some embodiments, a semiconductor structure includes a substrate, a dielectric region, a non-planar structure and a gate stack. The dielectric region is formed on the substrate, and has a top surface. The non-planar structure protrudes from the top surface, and includes a channel region, and source and drain regions formed on opposite sides of the channel region. The gate stack is formed on the top surface, wraps around the channel region, and includes a gate top surface, and a gate side wall that does not intersect the non-planar structure. The gate side wall has a first distance from a vertical plane at a level of the top surface, and a second distance from the vertical plane at a level of the gate top surface. The vertical plane is vertical with respect to the top surface, and intersects the non-planar structure. The first distance is shorter than the second distance.

Abstract: In some embodiments, a field effect transistor (FET) structure comprises a body structure, dielectric structures, a gate structure and a source or drain region. The gate structure is formed over the body structure. The source or drain region is embedded in the body structure beside the gate structure, and abuts and is extended beyond the dielectric structure. The source or drain region contains stressor material with a lattice constant different from that of the body structure. The source or drain region comprises a first region formed above a first level at a top of the dielectric structures and a second region that comprises downward tapered side walls formed under the first level and abutting the corresponding dielectric structures.