Patents by Inventor Yung Liang
Yung Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240146097Abstract: A vehicle power management system and an operating method thereof are provided. The vehicle power management system is adapted for a vehicle load device and a vehicle power supply, and includes a control circuit, a charge/discharge circuit and a backup battery. The control circuit is electrically connected to the vehicle power supply and the vehicle load device, and monitors an output voltage of the vehicle power supply and determines according to the output voltage whether a vehicle engine is started. The charge/discharge circuit is electrically connected to the control circuit and the backup battery. When the vehicle engine is started, the charge/discharge circuit supplies power of the vehicle power supply to the backup battery and the vehicle load device. When the vehicle engine is not started, the backup battery discharges the charge/discharge circuit and the charge/discharge circuit supplies power of the backup battery to the vehicle load device.Type: ApplicationFiled: March 8, 2023Publication date: May 2, 2024Inventors: YUNG-LE HUNG, CHENG-LIANG HUANG
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Patent number: 11973148Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.Type: GrantFiled: November 18, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
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Publication number: 20240130762Abstract: An artificial bone plate unit and an assembleable artificial bone plate are provided. The artificial bone plate unit includes a plate body, multiple connecting pins, connecting holes, drug cavities, and drug-releasing openings. The plate body has two main surfaces and a peripheral surface connected between the two main surfaces. The connecting pins and the connecting holes are formed on the plate body and arranged along the peripheral surface on the plate body. The connecting holes correspond in shape to the connecting pins. The drug cavities are formed in the artificial bone plate unit and are connected to the drug-releasing openings. The artificial bone plate units are connected using the connecting pins and the connecting holes to form the assembleable artificial bone plate. The assembleable artificial bone plate can be bent into the shape of a defect area of the skull, which saves material and time.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: Tung-Kuo TSAI, Keng-Liang OU, Yung-Kang SHEN, Yin-Chung HUANG, Kuo-Sheng HUNG, Yu-Sin OU
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Publication number: 20240136463Abstract: This disclosure discloses an optical sensing device. The device includes a carrier body; a first light-emitting device disposed on the carrier body; and a light-receiving device including a group III-V semiconductor material disposed on the carrier body, including a light-receiving surface having an area, wherein the light-receiving device is capable of receiving a first received wavelength having a largest external quantum efficiency so the ratio of the largest external quantum efficiency to the area is ?13.Type: ApplicationFiled: December 20, 2023Publication date: April 25, 2024Applicant: EPISTAR CORPORATIONInventors: Yi-Chieh LIN, Shiuan-Leh LIN, Yung-Fu CHANG, Shih-Chang LEE, Chia-Liang HSU, Yi HSIAO, Wen-Luh LIAO, Hong-Chi SHIH, Mei-Chun LIU
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Publication number: 20240136946Abstract: This patent presents a multidimensional space vector modulation (MDSVM) circuit formed by coupling a half-bridge logic control circuit not directly coupled to electronic components with at least three half-bridge logic control circuits coupled to electronic components. The half-bridge logic control circuit not directly coupled with any electronic components can form a full-bridge circuit with any other half-bridge logic control circuit coupled with electronic components. Therefore, users can further control the voltage difference between both ends of each electronic component separately and then individually control the strength and direction of current flowing through each electronic component and solving the problem of control attributed to the complexity of prior art.Type: ApplicationFiled: April 10, 2023Publication date: April 25, 2024Applicant: TENSOR TECH CO., LTDInventors: Shang Jung LEE, Po-Hsun YEN, Yung-Cheng CHANG, Sung-Liang HOU
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Publication number: 20240094464Abstract: A semiconductor-on-insulator (SOI) structure and a method for forming the SOI structure. The method includes forming a first dielectric layer on a first semiconductor layer. A second semiconductor layer is formed over an etch stop layer. A cleaning solution is provided to a first surface of the first dielectric layer. The first dielectric layer is bonded under the second semiconductor layer in an environment having a substantially low pressure. An index guiding layer may be formed over the second semiconductor layer. A third semiconductor layer is formed over the second semiconductor layer. A distance between a top of the third semiconductor layer and a bottom of the second semiconductor layer varies between a maximum distance and a minimum distance. A planarization process is performed on the third semiconductor layer to reduce the maximum distance.Type: ApplicationFiled: January 3, 2023Publication date: March 21, 2024Inventors: Eugene I-Chun Chen, Kuan-Liang Liu, De-Yang Chiou, Yung-Lung Lin, Chia-Shiung Tsai
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Patent number: 11928075Abstract: A method of transmitting data and command through an RS232 serial port incorporated with a user-end device and a server-end device connected through the RS232 serial port is disclosed and includes following steps: accumulating a value of a first counter of the user-end device and a value of a second counter of the server-end device whenever a data is transmitted from the server-end device to the user-end device; controlling the server-end device to stop transmitting the data and to wait when both of the two values reach a triggering threshold; controlling the user-end device to transmit a control command to the server-end device through the RS232 serial port while the server-end device is waiting; and, resetting the first and the second counter and controlling the server-end device to restore to transmit the data to the user-end device after a waiting time is elapsed.Type: GrantFiled: June 22, 2022Date of Patent: March 12, 2024Assignee: DELTA ELECTRONICS, INC.Inventor: Yung-Liang Chang
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Patent number: 11923433Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.Type: GrantFiled: March 9, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
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Publication number: 20230366925Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11778839Abstract: Provided is a perovskite film including crystal grains with a crystalline structure of [A][B][X]3.n[C], wherein [A], [B], [X], [C] and n are as defined in the specification. The present disclosure further provides a precursor composition of perovskite film, method for producing of perovskite film, and semiconductor element including such films, as described above. With the optimal lattice arrangement, the perovskite film shows the effects of small surface roughness, and the semiconductor element thereof can thus achieve high efficiency and stability even with large area of film formation, thereby indeed having prospect of the application.Type: GrantFiled: December 15, 2020Date of Patent: October 3, 2023Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Kuo-Wei Huang, Yung-Liang Tung, Jung-Pin Chiou, Pei-Ting Chiu, Shih-Hsiung Wu
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Publication number: 20230289316Abstract: A method of transmitting data and command through an RS232 serial port incorporated with a user-end device and a server-end device connected through the RS232 serial port is disclosed and includes following steps: accumulating a value of a first counter of the user-end device and a value of a second counter of the server-end device whenever a data is transmitted from the server-end device to the user-end device; controlling the server-end device to stop transmitting the data and to wait when both of the two values reach a triggering threshold; controlling the user-end device to transmit a control command to the server-end device through the RS232 serial port while the server-end device is waiting; and, resetting the first and the second counter and controlling the server-end device to restore to transmit the data to the user-end device after a waiting time is elapsed.Type: ApplicationFiled: June 22, 2022Publication date: September 14, 2023Inventor: Yung-Liang CHANG
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Patent number: 11754621Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: GrantFiled: June 29, 2022Date of Patent: September 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20230251306Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: ApplicationFiled: April 17, 2023Publication date: August 10, 2023Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11630149Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.Type: GrantFiled: June 21, 2021Date of Patent: April 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
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Publication number: 20230102199Abstract: Provided is a method for preparing lead iodide, which controls the crystal form of lead iodide through temperature, including: dissolving a lead compound in a first acid solution and adding an iodine compound to form a reaction solution including the first lead iodide; and heating the reaction solution to a temperature of 60° C. or more and standing at a constant temperature, to obtain the second lead iodide, wherein a peak intensity of the (003) crystal plane of the second lead iodide is greater than or equal to a peak intensity of the (110) crystal plane. Provided is also a method for preparing the perovskite film.Type: ApplicationFiled: January 12, 2022Publication date: March 30, 2023Inventors: Pei-Ting Chiu, Yung-Liang Tung, Shih-Hsiung Wu, Kuo-Wei Huang, Jung-Pin Chiou, Jen-An Chen, Qiao-Zhi Guan
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Publication number: 20230079784Abstract: Provided is a method for testing a perovskite precursor solution, including: taking a perovskite precursor solution containing a plurality of dispersed perovskite colloids as a sample to perform liquid analysis, thereby obtaining an analysis information; and determining whether the perovskite precursor solution is a good product based on obtained analysis information from the liquid analysis, wherein the analysis information is at least one selected from the group consisting of element content of the colloid, element distribution, colloid size, and colloid appearance, thereby a feasible and effective testing method is defined through the correlation between the perovskite precursor colloid and the perovskite.Type: ApplicationFiled: November 17, 2021Publication date: March 16, 2023Inventors: Kuo-Wei Huang, Pei-Ting Chiu, Yung-Liang Tung, Po-Tsung Hsieh, Tai-Fu Lin
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Patent number: 11528592Abstract: A method for robust moving between a roaming Third Generation Partnership Project (3GPP) network and a non-3GPP network is provided. The method includes the steps of: connecting with a home 3GPP network over one of a roaming 3GPP network and a non-3GPP network by a User Equipment (UE); performing a first initial attach procedure with the home 3GPP network over the other of the roaming 3GPP network and the non-3GPP network by the UE in response to the UE moving from the one of the roaming 3GPP network and the non-3GPP network to the other of the roaming 3GPP network and the non-3GPP network; and keeping the connection over the one of the roaming 3GPP network and the non-3GPP network by the UE during the first initial attach procedure over the other of the roaming 3GPP network and the non-3GPP network.Type: GrantFiled: August 3, 2020Date of Patent: December 13, 2022Assignee: MEDIATEK INC.Inventors: Yung-Liang Tsou, Hao-Chen Chou, Szu-Chieh Chiu, Chien-Yi Wang, Rohit Naik
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Publication number: 20220326300Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
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Patent number: 11461076Abstract: A method for editing continual vertical line of visual programming language includes following steps: entering an editing mode; selecting a source node as a current node from a serial-parallel graphic where the source node is an endpoint of one of a plurality of normal blocks in the graphic; calculating and displaying one or more candidate nodes around current node; connecting the current node to any one of the candidate nodes for converting the connected candidate node into a connected node; setting the connected node as the current node for continually calculating, displaying, connecting to one or more candidate nodes before exiting the editing mode; generating a continual vertical line according to the source node and the one or more connected nodes when exiting the editing mode; modifying the serial-parallel relationship among the plurality of normal blocks in the graphic and updating the graphic according to the continual vertical line.Type: GrantFiled: September 28, 2020Date of Patent: October 4, 2022Assignee: DELTA ELECTRONICS, INC.Inventors: Yung-Liang Chang, Mao-Hua Cheng, Kuei-Fu Liu