Patents by Inventor Yung Liang

Yung Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220326300
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 13, 2022
    Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
  • Patent number: 11461076
    Abstract: A method for editing continual vertical line of visual programming language includes following steps: entering an editing mode; selecting a source node as a current node from a serial-parallel graphic where the source node is an endpoint of one of a plurality of normal blocks in the graphic; calculating and displaying one or more candidate nodes around current node; connecting the current node to any one of the candidate nodes for converting the connected candidate node into a connected node; setting the connected node as the current node for continually calculating, displaying, connecting to one or more candidate nodes before exiting the editing mode; generating a continual vertical line according to the source node and the one or more connected nodes when exiting the editing mode; modifying the serial-parallel relationship among the plurality of normal blocks in the graphic and updating the graphic according to the continual vertical line.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: October 4, 2022
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yung-Liang Chang, Mao-Hua Cheng, Kuei-Fu Liu
  • Patent number: 11448692
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: September 20, 2022
    Assignee: TAIWANN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Publication number: 20220244521
    Abstract: A sight adjusting mechanism includes an adjusting knob, an adjusting ring member, an adjusting bolt and a base. An upper-side portion of the adjusting bolt enters a through hole of the adjusting ring member to couple with the adjusting ring member. A lower-side portion of the adjusting bolt enters a through hole of the base to couple with the base. Thus, the adjusting bolt can only move along an axis. The mechanism is implemented without mechanical feedback, and thus rotating angles are improved with great precision. Also, the mechanism includes a limiting member disposed in a penetrating hole of the adjusting knob and a positioning ring mounted on the adjusting ring member. By cooperation of the limiting member and the positioning ring, an angle at which the adjusting knob can rotate is defined. A fine adjustment and a quick adjustment of a sight point are implemented.
    Type: Application
    Filed: January 27, 2022
    Publication date: August 4, 2022
    Applicants: SINTAI OPTICAL (SHENZHEN) CO., LTD., ASIA OPTICAL CO., INC.
    Inventor: Shang-yung Liang
  • Patent number: 11405093
    Abstract: A wireless device comprises a transceiving circuit, configured to receive a plurality of beam performance parameters corresponding to a plurality beams; a storage circuit, configured to store a table, wherein corresponding relationships between the plurality beams and the plurality of beam performance parameters are tabulated in the table; and a processing circuit, configured to perform the following steps: selecting a first beam according to the table; determining whether a first beam performance value corresponding to the first beam is less than a threshold; and selecting a second beam according to the table when the first beam performance value is less than the threshold.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 2, 2022
    Assignee: Wistron NeWeb Corporation
    Inventors: Yung-Liang Huang, Wen-Jiun Lin
  • Publication number: 20220123242
    Abstract: Provided is a perovskite film including crystal grains with a crystalline structure of [A][B][X]3.n[C], wherein [A], [B], [X], [C] and n are as defined in the specification. The present disclosure further provides a precursor composition of perovskite film, method for producing of perovskite film, and semiconductor element including such films, as described above. With the optimal lattice arrangement, the perovskite film shows the effects of small surface roughness, and the semiconductor element thereof can thus achieve high efficiency and stability even with large area of film formation, thereby indeed having prospect of the application.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 21, 2022
    Inventors: Kuo-Wei Huang, Yung-Liang Tung, Jung-Pin Chiou, Pei-Ting Chiu, Shih-Hsiung Wu
  • Patent number: 11271157
    Abstract: Provided are a perovskite film and a manufacturing method thereof. The method includes the following steps. A perovskite precursor material is coated in a linear direction on a substrate with a temperature between 100° C. and 200° C., wherein a concentration of the perovskite precursor material is between 0.05 M and 1.5 M. An infrared light irradiation is performed on the perovskite precursor material to cure the perovskite precursor material to form a thin film including a compound represented by formula (1). The perovskite film has a single 2D phase structure or has a structure in which a 3D phase structure is mixed with a single 2D phase structure. (RNH3)2MA(n?1)M1nX(3n+1)??formula (1), wherein the definitions of R, MA, M1, X, and n are as defined above.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 8, 2022
    Assignee: Industrial Technology Research Institute
    Inventors: Kuo-Wei Huang, Yung-Liang Tung, Shih-Hsiung Wu, Jen-An Chen, Pei-Ting Chiu, Yu-Hung Chen
  • Publication number: 20220069221
    Abstract: Provided are a perovskite film and a manufacturing method thereof. The method includes the following steps. A perovskite precursor material is coated in a linear direction on a substrate with a temperature between 100° C. and 200° C., wherein a concentration of the perovskite precursor material is between 0.05 M and 1.5 M. An infrared light irradiation is performed on the perovskite precursor material to cure the perovskite precursor material to form a thin film including a compound represented by formula (1). The perovskite film has a single 2D phase structure or has a structure in which a 3D phase structure is mixed with a single 2D phase structure. (RNH3)2MA(n?1)M1nX(3n+1)??formula (1), wherein the definitions of R, MA, M1, X, and n are as defined above.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 3, 2022
    Applicant: Industrial Technology Research Institute
    Inventors: Kuo-Wei Huang, Yung-Liang Tung, Shih-Hsiung Wu, Jen-An Chen, Pei-Ting Chiu, Yu-Hung Chen
  • Publication number: 20220038885
    Abstract: A method for robust moving between a roaming Third Generation Partnership Project (3GPP) network and a non-3GPP network is provided. The method includes the steps of: connecting with a home 3GPP network over one of a roaming 3GPP network and a non-3GPP network by a User Equipment (UE); performing a first initial attach procedure with the home 3GPP network over the other of the roaming 3GPP network and the non-3GPP network by the UE in response to the UE moving from the one of the roaming 3GPP network and the non-3GPP network to the other of the roaming 3GPP network and the non-3GPP network; and keeping the connection over the one of the roaming 3GPP network and the non-3GPP network by the UE during the first initial attach procedure over the other of the roaming 3GPP network and the non-3GPP network.
    Type: Application
    Filed: August 3, 2020
    Publication date: February 3, 2022
    Inventors: Yung-Liang TSOU, Hao-Chen CHOU, Szu-Chieh CHIU, Chien-Yi WANG, Rohit NAIK
  • Publication number: 20210360838
    Abstract: The present disclosure provides a composite material for shielding or absorbing an electromagnetic wave and a method for manufacturing the same. The composite material includes an electromagnetic absorbing material including a silicon carbide and a conductive material including a two-dimensional carbon material containing at least one of a graphite sheet and a graphene sheet.
    Type: Application
    Filed: June 24, 2020
    Publication date: November 18, 2021
    Applicant: GET Green Energy Corp., Ltd.
    Inventors: Wei-Jen Liu, Hsi-Nien Ho, I-Ting Hsieh, Cheng-Che Hsieh, Yung-Liang Ke, Yun Shuan Chu
  • Patent number: 11177598
    Abstract: A full-shielding cable connector includes an insulated body, a metal frame, a shielding conductive body, and a pull rod. The insulated body has a plurality of terminal slots for receiving a plurality of terminals, respectively. The metal frame is fixed to the insulated body. The metal frame has pins that are electrically connected to a grounding circuit of a circuit board. The shielding conductive body is detachably assembled to the insulated body and arranged above the metal frame. The shielding conductive body has a cable receiving chamber for receiving a cable, and contacts a top and bottom surface of the cable. The pull rod is rotatable with respect to the shielding conductive body. The pull rod can be rotated to a front end of the insulated body to be fastened thereto.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: November 16, 2021
    Assignee: BELLWETHER ELECTRONIC CORP.
    Inventor: Yung-Liang Chi
  • Publication number: 20210311110
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
  • Patent number: 11073551
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations. A wafer having an IC formed thereon is provided. The IC is energized by raising the voltage of the IC to a first voltage level during a first period. A stress signal is applied to the IC. The stress signal includes a plurality of sequences during a second period subsequent to the first period. Each of the sequence has a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level. Whether the IC complies with a test criterion is determined after applying the stress signal.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Jun He, Yu-Ting Lin, Wei-Hsun Lin, Yung-Liang Kuo, Yinlung Lu
  • Publication number: 20210199710
    Abstract: The present disclosure provides a method and a system for testing semiconductor device. The method includes providing a device under test (DUT) having an input terminal and an output terminal; applying a voltage having a first voltage level to the input terminal of the DUT during a first period; applying a stress signal to the input terminal of the DUT during a second period subsequent to the first period; obtaining an output signal in response to the stress signal at the output terminal of the DUT; and comparing the output signal with the stress signal. The stress signal includes a plurality of sequences, each having a ramp-up stage and a ramp-down stage. The stress signal has a second voltage level and a third voltage level.
    Type: Application
    Filed: March 11, 2021
    Publication date: July 1, 2021
    Inventors: JUN HE, YU-TING LIN, WEI-HSUN LIN, YUNG-LIANG KUO, YINLUNG LU
  • Publication number: 20210175425
    Abstract: Provided are a method for forming a perovskite layer and a method for forming a structure comprising a perovskite layer. The method for forming a perovskite layer includes the following steps: coating a perovskite precursor material on a substrate; and performing a heating treatment to the substrate; and irradiating the perovskite precursor material with infrared light.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 10, 2021
    Applicant: Industrial Technology Research Institute
    Inventors: Shih-Hsiung Wu, Yung-Liang Tung, Kuo-Wei Huang, Pei-Ting Chiu, Hung-Ru Hsu, Jia-Ming Lin
  • Publication number: 20210145194
    Abstract: The invention relates to a hotpot ware. The hotpot ware includes a basin-shaped main body adapted for holding and heating a liquid foodstuff, wherein the main body defines a top opening and is integrally formed with a radially outwardly extending rim along the top opening; a dry ice reservoir mounted on and adapted for heat exchange with the rim; and a passageway connected to the dry ice reservoir and adapted for discharge of gasified dry ice. By establishing a heat exchange relationship between the basin-shaped main body and the dry ice reservoir, dry ice accommodated in the dry ice reservoir would rapidly sublimates as the basin-shaped main body is heated, and then a large amount of white vaporous carbon dioxide gas is discharged outward through the passageway, thereby creating an amazing visual effect.
    Type: Application
    Filed: January 21, 2020
    Publication date: May 20, 2021
    Inventor: Yung-Liang CHEN
  • Publication number: 20210149642
    Abstract: A method for editing continual vertical line of visual programming language includes following steps: entering an editing mode; selecting a source node as a current node from a serial-parallel graphic where the source node is an endpoint of one of a plurality of normal blocks in the graphic; calculating and displaying one or more candidate nodes around current node; connecting the current node to any one of the candidate nodes for converting the connected candidate node into a connected node; setting the connected node as the current node for continually calculating, displaying, connecting to one or more candidate nodes before exiting the editing mode; generating a continual vertical line according to the source node and the one or more connected nodes when exiting the editing mode; modifying the serial-parallel relationship among the plurality of normal blocks in the graphic and updating the graphic according to the continual vertical line.
    Type: Application
    Filed: September 28, 2020
    Publication date: May 20, 2021
    Inventors: Yung-Liang CHANG, Mao-Hua CHENG, Kuei-Fu LIU
  • Patent number: 10987909
    Abstract: The present invention provides a method of laminating a film for a dye-sensitized cell. First, a composite film is taken by a robotic arm, in which the composite film includes a release layer, a protective layer and a hot glue layer between the release layer and the protective layer, and the release layer is removed by the robotic arm. Then, the hot glue layer is precisely attached to a substrate by a target positioning step. Next, the protective layer is removed by the robotic arm.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: April 27, 2021
    Assignee: FORMOSA PLASTICS CORPORATION
    Inventors: Ching-Fu Chen, Hao-Wei Chen, Kun-Tai Ho, Wan-Tun Hung, Po-Min Chen, Liang-Kun Huang, Chih-Chou Chang, Yung-Liang Tung, Po-Tsung Hsiao, Ming-De Lu
  • Patent number: D917288
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: April 27, 2021
    Inventor: Yung-Liang Chen
  • Patent number: D963416
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 13, 2022
    Inventor: Yung-Liang Chen