Abstract: A method for system for dynamic channel Log Likelihood Ratio (LLR) quantization for a Solid State Drive (SSD) controller is a targeted approach to scaling which results in a scaled, quantized set of LLRs whose relative magnitude remains undisturbed from an original magnitude. The method reads a set of voltages from each channel of the SSD. The set of reads is configured in location and number for performance. Once a set is returned, the method determines an LLR for each of the voltages read resulting in a raw set of LLRs. Targeted scaling results in a scaled set of LLRs between an upper limit and a lower limit determined for reading by a decoder. Once scaled, the LLRs are rounded and quantized for use by the decoder to produce an Error Correction Code (ECC).

Abstract: A method of optimizing solid state drive (SSD) soft retry voltages comprises limiting a number of voltage reads and properly spacing and determining the reference voltage at which each voltage is read based on desired Bit Error Rate (BER) and channel throughput. The method determines each reference voltage for a number of soft retry voltage reads based on a hard decision read. The spacing between each read reference voltage is constant since each SSD type requires a number of reads for an accurate presentation of soft retry voltages. The voltage distance between each successive read is limited to a multiple of the constant spacing while the multiple is based on success or failure of the first read. The method determines a limited number of reads, the constant spacing between reads, and a desired reference voltage for each read, thereby increasing valuable throughput of the channel and decreasing BER.

Abstract: A method and apparatus for generating soft decision error correction code information. The method includes generating or creating a lookup table (LUT), such as a log likelihood ratio (LLR) lookup table, characterizing a flash memory device. The method also includes loading the lookup table into the SSD controller. The method also includes accessing the lookup table to assign LLR or other characteristic values to the cells of a flash memory device. The method also includes decoding the data in a flash memory device using the soft decision information provided by the lookup table and assigned to the appropriate cells of the flash memory device.

Abstract: A method for applying a sequence of sensing/read reference voltages in a read channel includes (A) setting a read window based on an estimate of a read channel, (B) setting first, second, and third values of a sequence of sensing voltages to values corresponding to different ones of (i) a left-hand limit of the read window, (ii) a right-hand limit of the read window; and (iii) a point central to the read window, (C) determining whether first, second and third reads are successful, and (D) if the first, second and third reads are not successful, setting fourth and fifth values of the sequence of sensing voltages to values corresponding to different ones of (i) a point between the left-hand limit and the point central to the read window and (ii) a point between the right-hand limit and the point central to the read window.

Abstract: Methods and apparatus are provided for computing reliability values, such as log likelihood ratios (LLRs), with reduced complexity for flash memory devices. Data from a flash memory device that stores M bits per cell using 2?M possible states is processed by obtaining at least two soft read voltage values corresponding to two reference voltages V0 and V1, wherein the two reference voltages V0 and V1 are between two adjacent states of the 2?M possible states; and converting the at least two soft read voltage values to a log likelihood ratio for a region between the two reference voltages V0 and V1 using probability density functions only for the two adjacent states. The soft read voltage values comprise, for example, hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and/or soft values obtained from the flash memory device.

Abstract: An apparatus comprising a memory configured to store data and a controller. The controller may be configured to process a plurality of input/output requests to read/write to/from the memory. The controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether the read is successful, (iii) if the read is not successful, perform a plurality of reads with a varying value of the threshold voltage, (iv) read a calibration value from a look-up table based on the plurality of reads and (v) set the threshold value in response to the calibration value.

Abstract: The disclosure is directed to a system and method for nominal read voltage variations of a flash device. N reads are performed, each at a selected voltage offset from an initial read voltage. An N bit digital pattern associated with the selected voltage offsets is generated for the N reads. The N bit digital pattern generated by the N reads is mapped to a signed representation. A voltage adjustment based upon the signed representation is applied to at least partially compensate for a variation of the nominal read voltage to reduce bit error rate of the flash device.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate an output signal in response to (i) a value retrieved from a look-up table, and (ii) an index signal. The second circuit may be configured to generate the index signal in response to a plurality of page signals. The apparatus may manage decision patterns during a soft retry.

Abstract: An apparatus having a circuit and one or more processor is disclosed. The circuit is configured to receive a codeword from a memory. The memory is nonvolatile. The codeword generally has one or more errors. The processors are configured to generate read data by decoding the codeword repeatedly. The decoding includes a soft-decision decoding that uses a plurality of parameters calculated by (i) a first procedure, (ii) a second procedure in response to a plurality of failures of the decoding to converge using the first procedure and (iii) a third procedure in response to another failure of the decoding to converge using the second procedure.

Abstract: Mixed-granularity higher-level redundancy for NVM provides improved higher-level redundancy operation with better error recovery and/or reduced redundancy information overhead. For example, pages of the NVM that are less reliable, such as relatively more prone to errors, are operated in higher-level redundancy modes having relatively more error protection, at a cost of relatively more redundancy information. Concurrently, blocks of the NVM that are more reliable are operated in higher-level redundancy modes having relatively less error protection, at a cost of relatively less redundancy information. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively less error protection, techniques described herein provide better error recovery. Compared to techniques that operate the entirety of the NVM in the higher-level redundancy modes having relatively more error protection, the techniques described herein provide reduced redundancy information overhead.

Abstract: In an SSD controller reading from flash memory, subsequent to failure of an initial soft-decision decoding attempt based on a nominal LLR, soft-decision re-decoding attempts are made using compensated LLR soft-decision information sets, pre-calculated at respective read-equilibrium points corresponding to mean shifts and variance change in the actual charge-state distributions of the flash memory channel. According to embodiment, soft-decision re-decoding attempts are performed without a retry read, or overlapped with one or more retry reads. By overlapping re-decoding with one or more retry reads, the probability of successful decoding increases, the need for further retry reads diminishes, and throughput is improved. The LLR compensation becomes very effective over a large number of retry reads, improving decoding reliability and achieving close to optimal bit error rates, even in the presence of large channel variation.

Abstract: A Solid-State Disk (SSD) controller performs soft-decision decoding with a single read, thus improving performance, power, and/or reliability of a storage sub-system, such as an SSD. In a first aspect, the controller generates soft-decision metrics from channel parameters of a hard decode read, without additional reads and/or array accesses. In a second aspect, the controller performs soft decoding using the generated soft-decision metrics. In a third aspect, the controller generates soft-decision metrics and performs soft decoding with the generated soft-decision metrics when a hard decode read error occurs.

Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate a reference voltage used by a memory circuit in a first read of a set of data and (ii) adjust the reference voltage based on a plurality of parameters to lower an error rate in a second read of the set from the memory circuit. The second circuit may be configured to update the parameters in response to an error correction applied to the set after the first read from the memory circuit. The memory circuit is generally configured to store the data in a nonvolatile condition by adjusting a plurality of threshold voltages.

Abstract: A hard disk drive with a read channel that averages data before the data is provided to a viterbi detector of the channel. Averaging the data reduces the zero mean noise in the data.

Abstract: A hard disk drive with a read channel that averages data before the data is provided to a viterbi detector of the channel. Averaging the data reduces the zero mean noise in the data.

Abstract: A method for providing data to determine an optimal track per inch (“TPI”) density for a head of a hard disk drive. The method utilizes a VGA control signal that is used in an automatic gain control loop of the disk drive. First VGA values are stored during a routine where a head reads the disk at different offset positions across an N track. The head is then moved to an offset position of an adjacent track N+1 and then erases at least a portion of the N+1 track. Second VGA values are then stored as the head again reads the N track at different offset positions of the track. This process is repeated for a plurality of different TPI values. The effective head width is determined from the second VGA values are plotted relative to different TPI values. An optimum TPI value can be determined from this plot.

Abstract: A method for providing data to determine an optimal track per inch (“TPI”) density for a head of a hard disk drive. The method utilizes a VGA control signal that is used in an automatic gain control loop of the disk drive. First VGA values are stored during a routine where a head reads the disk at different offset positions across an N track. The head is then moved to an offset position of an adjacent track N+1 and then erases at least a portion of the N+1 track. Second VGA values are then stored as the head again reads the N track at different offset positions of the track. This process is repeated for a plurality of different TPI values. The effective head width is determined from the second VGA values are plotted relative to different TPI values. An optimum TPI value can be determined from this plot.