Abstract: A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.

Abstract: An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.

Abstract: An implant is added at the interface between the source region of an MOS transistor and the well material to improve dynamic IR drop performance. The additional implant raises the underlying capacitance of the source region. This, in turn, provides for an increase in charge storage which, in turn, provides for an improved level of protection against dynamic IR drop.

Abstract: In a method and structure for a high voltage LDMOS with reduced hot carrier degradation, the thick field oxide is eliminated and a reduced surface field achieved instead by including adjacent p+ and n+ regions in the drain well and shorting these regions to each other, or by including a p+ region in the drain well and biasing it to a positive voltage relative to the source voltage.

Abstract: A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.

Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

Abstract: An SCR device having a first P type region disposed in a semiconductor body and electrically connected to anode terminal of the device. At least one N type region is also disposed in the body adjacent the first P type region so as to form a PN junction having a width Wn near a surface of the semiconductor body. A further P type region is also disposed in the body to form a further PN junction with the N type region, with the junction having a width Wp near the body surface, with Wp being at least 1.5 times width Wn. A further N type region is provided which is electrically connected to a cathode terminal of the device and forming a third PN junction with the further N type region.

Abstract: NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.

Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

Abstract: A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.

Abstract: Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal.

Abstract: A charge pump circuit in which at least one of the switching elements takes the form of a LVTSCR. The switching on and off of the LVTSCRs may be achieved by making use of a pulsed input and relying on the triggering and holding voltages of the LVTSCRs to switch on and off.

Abstract: A method of selectively programming nonvolatile memory cells in which multiple programming voltages are used to obtain the desired voltage on the storage nodes of the cells selected for programming, while the storage nodes of unselected cells remain undisturbed.

Abstract: A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

Abstract: An integrated nonvolatile memory circuit having a plurality of control devices. Separate devices execute distinct control, erase, write and read operations, thereby allowing each device to be individually selected and optimized for performing its respective operation.

Abstract: A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.

Abstract: A programming technique for a one-time-programmable non-volatile memory (NVM) utilizes a repeated programming cycle with an interval between cycles that is long enough to redistribute charge in the layers surrounding the floating gate of the cell. Each cycle programs the floating gate and also the surrounding layers. The cycling saturates in an equilibrium state when the electric field form outside to the floating gate equals zero. This technique eliminates the first stage of conventional VT drop in NVM cells and, thus, improves retention.

Abstract: An active pixel sensor cell including at least one photodiode and reset circuitry and an integrating varactor coupled to the photodiode, a method for reading out such a cell, and an image sensor including an array of such cells. The photodiode can be exposed to photons during an exposure interval to accumulate a sequence of subexposure charges at a first node of the photodiode. Each of the subexposure charges accumulates at the first node during a different subexposure interval of the exposure interval. The photodiode is reset during each of a sequence of reset intervals, each reset interval occurring before a different one of the subexposure intervals. An output signal indicative of an exposure charge accumulated at the storage node during the exposure interval can be asserted from the cell, where the exposure charge is indicative of a sum of all the subexposure charges.

Abstract: A method is provided for erasing a nonvolatile memory cell that includes a source region, a drain region, a floating gate electrode and a control gate electrode to which an erase signal is applied. In accordance with the method, a source bias voltage is applied to the source region, a drain bias voltage is applied to the drain region, and a frequency/time domain based voltage signal is applied to the control gate electrode of the cell as the erase signal.

Abstract: A method of programming a PMOS stacked gate memory cell is provided that utilizes a sequence of control gate pulses to obtain the desired potential on the floating gate.