Abstract: A transceiver includes an array of pMUT elements, where each pMUT element includes: a substrate; a membrane suspending from the substrate; a bottom electrode disposed on the membrane; a piezoelectric layer disposed on the bottom electrode; and a first electrode disposed on the piezoelectric layer. Each pMUT element exhibits one or more modes of vibration.

Abstract: An imaging system includes: a transceiver cell for generating a pressure wave and converting an external pressure wave into an electrical signal; and a control unit for controlling an operation of the transceiver cell. The transceiver cell includes: a substrate; at least one membrane suspending from the substrate; and a plurality of transducer elements mounted on the at least one membrane. Each of the plurality of transducer elements has a bottom electrode, a piezoelectric layer on bottom electrode, and at least one top electrode on the piezoelectric layer. Each of the plurality of transducer element generates a bending moment in response to applying an electrical potential across the bottom electrode and the at least one top electrode and develops an electrical charge in response to a bending moment due to the external pressure wave.

Abstract: Described are transducer assemblies and imaging devices comprising: a microelectromechanical systems (MEMS) die including a plurality of piezoelectric elements; a complementary metal-oxide-semiconductor (CMOS) die electrically coupled to the MEMS die by a first plurality of bumps and including at least one circuit for controlling the plurality of piezoelectric elements; and a package secured to the CMOS die by an adhesive layer and electrically connected to the CMOS die.

Abstract: A transducer assembly includes: a microelectromechanical systems (MEMS) die including a plurality of piezoelectric elements; a complementary metal-oxide-semiconductor (CMOS) die electrically coupled to the MEMS die by a first plurality of bumps and including at least one circuit for controlling the plurality of piezoelectric elements; and a package secured to the CMOS die by an adhesive layer and electrically connected to the CMOS die.

Abstract: An imaging device includes a two dimensional array of piezoelectric elements. Each piezoelectric element includes: a piezoelectric layer; a bottom electrode disposed on a bottom side of the piezoelectric layer and configured to receive a transmit signal during a transmit mode and develop an electrical charge during a receive mode; and a first top electrode disposed on a top side of the piezoelectric layer; and a first conductor, wherein the first top electrodes of a portion of the piezoelectric elements in a first column of the two dimensional array are electrically coupled to the first conductor.

Abstract: An imaging device includes a two dimensional array of piezoelectric elements. Each piezoelectric element includes: a piezoelectric layer; a bottom electrode disposed on a bottom side of the piezoelectric layer and configured to receive a transmit signal during a transmit mode and develop an electrical charge during a receive mode; and a first top electrode disposed on a top side of the piezoelectric layer; and a first conductor, wherein the first top electrodes of a portion of the piezoelectric elements in a first column of the two dimensional array are electrically coupled to the first conductor.

Abstract: An imaging device includes a two dimensional array of piezoelectric elements. Each piezoelectric element includes: a piezoelectric layer; a bottom electrode disposed on a bottom side of the piezoelectric layer and configured to receive a transmit signal during a transmit mode and develop an electrical charge during a receive mode; and a first top electrode disposed on a top side of the piezoelectric layer; and a first conductor, wherein the first top electrodes of a portion of the piezoelectric elements in a first column of the two dimensional array are electrically coupled to the first conductor.

Abstract: A transducer assembly includes: a microelectromechanical systems (MEMS) die including a plurality of piezoelectric elements; a complementary metal-oxide-semiconductor (CMOS) die electrically coupled to the MEMS die by a first plurality of bumps and including at least one circuit for controlling the plurality of piezoelectric elements; and a package secured to the CMOS die by an adhesive layer and electrically connected to the CMOS die.

Abstract: An imaging system includes: a transceiver cell for generating a pressure wave and converting an external pressure wave into an electrical signal; and a control unit for controlling an operation of the transceiver cell. The transceiver cell includes: a substrate; at least one membrane suspending from the substrate; and a plurality of transducer elements mounted on the at least one membrane. Each of the plurality of transducer elements has a bottom electrode, a piezoelectric layer on bottom electrode, and at least one top electrode on the piezoelectric layer. Each of the plurality of transducer element generates a bending moment in response to applying an electrical potential across the bottom electrode and the at least one top electrode and develops an electrical charge in response to a bending moment due to the external pressure wave.

Abstract: An imaging device includes a two dimensional array of piezoelectric elements. Each piezoelectric element includes: a piezoelectric layer; a bottom electrode disposed on a bottom side of the piezoelectric layer and configured to receive a transmit signal during a transmit mode and develop an electrical charge during a receive mode; and a first top electrode disposed on a top side of the piezoelectric layer; and a first conductor, wherein the first top electrodes of a portion of the piezoelectric elements in a first column of the two dimensional array are electrically coupled to the first conductor.

Abstract: A transceiver includes an array of pMUT elements, where each pMUT element includes: a substrate; a membrane suspending from the substrate; a bottom electrode disposed on the membrane; a piezoelectric layer disposed on the bottom electrode; and a first electrode disposed on the piezoelectric layer. Each pMUT element exhibits one or more modes of vibration.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a dock signal for each of the plurality of ADCs such that edges of said clock signals trigger sampling of an input signal by the plurality of ADCs; and a timing adjustment circuit to receive and adjust the dock signals before the dock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and a random number generator to pseudo randomly select which ADC samples the input signal; and a circuit for adjusting the bandwidth of the plurality of ADCs.

Abstract: A time-interleaved Analog-to-Digital Converter (ADC) includes a set of time multiplexed sub-ADC circuits, each sub-ADC circuit comprising a sample-and-hold circuit. Each sample-and-hold circuit includes a bootstrap circuit for maintaining a constant voltage level between an input terminal of a switch and a gate terminal of the switch, the switch for switching between a track mode and a hold mode, and a capacitor bank associated with the bootstrap circuit such that a setting of the capacitor bank affects the voltage level.

Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.

Abstract: A pipelined Analog-to-Digital Converter (ADC) stage includes a main sampling path having a first filter in series with a first sample and hold circuit and a sub-ADC sampling path having a second filter in series with a second sample and hold circuit driving a sub-ADC connected to a sub-Digital-to-Analog Converter (DAC). The frequency response of the main sampling path is matched to a frequency response of the sub-ADC sampling path such that a residue signal of the pipelined ADC stage stays within range.

Abstract: A time-interleaved sample-and-hold system includes a first sample-and-hold circuit and a second sample-and-hold circuit. The first sample-and-hold circuit and the second sample-and-hold circuit share a common sampling switch. A method of remediating a timing offset between a first sample-and-hold circuit and a second sample-and-hold circuit in a time-interleaved sample-and-hold system includes switching at least one shunt capacitor disposed between two logic gates in a timing circuit to adjust a delay between a timing signal for a common sampling switch electrically coupled to the first and second sample-and-hold circuits and a timing signal for at least one of the sample-and-hold circuits.