Abstract: A carrier detection circuit includes a rectification stage, an integrator, a comparator, and a digital counter. By utilizing a digital counter, long time constants are provided without the use of external components. If desired, a mark detect circuit is used when a mark must be present to signify the presence of carrier. Hysteresis is provided by the comparator to insure that slight fluctuations in the carrier level do not affect the comparison.

Abstract: An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.

Abstract: A differential operational amplifier is provided with a feedback loop which continuously adjusts the common mode voltage level of the amplifier so that it lies in the center of the dynamic range of the amplifier. The feedback loop measures the instantaneous common mode voltage level and compares it with a reference voltage which is set to reflect the desired common mode voltage. An error signal is generated and fed back into the amplifier to adjust the instantaneous common mode voltage level towards the reference level. Frequency compensation is also provided to overcome the phase shift introduced by the use of RC networks.

Abstract: A programmable transversal filter utilizes a plurality of programmable multiplying means. The result of each multiplication is summed by a summing circuit, thus providing an output signal. The delay network comprises a plurality of signal sample and hold circuits which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods. The filter also includes a plurality of reference sample and hold circuits which store error voltages equal to the error voltage component of the voltages provided by the signal sample and hold circuits.A first analog cross-point switch is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.

Abstract: A programmable transversal filter (10) utilizes a plurality of programmable multiplying means (M.sub.1 -M.sub.4). The result of each multiplication is summed by a summing circuit (7), thus providing an output signal (y(t)). The delay network of this invention comprises a plurality of sample and hold circuits (S.sub.1 -S.sub.4) which are selectively connected to the input bus in sequence, in order that one sample and hold circuit may store an analog signal sampled during the present time instant, with other sample and hold circuits storing a plurality of analog signals each of which has been sampled during a corresponding one of a plurality of preceding sample periods.An analog cross-point switch (51) is utilized wherein each of said plurality of time delayed analog signals may be selectively applied to a selected multiplying means.

Abstract: An operational amplifier has one noninverting input lead (116), and two inverting input leads (117a, 117b). One of these inverting input leads (117a) is utilized to compensate for the effects of the inherent offset voltage (V.sub.off) of the operational amplifier, and the second inverting input lead (117b) receives an input signal to be amplified or compared.

Abstract: An AGC circuit (12) contains a programmable gain stage comprising an operational amplifier (150) and one or more capacitor arrays (101, 121) for controlling the closed loop gain of the operational amplifier. The output signal (V.sub.O) of this operational amplifier is rectified, and the rectified signal is alternately integrated with a reference voltage (V.sub.ref) of opposite polarity to the rectified AGC signal. The polarity of the integrated voltages operates a counter stage (200). The output bits (0.sub.2 -0.sub.N) of the counter are used to control switches (134-2 through 134-N, 135-2 through 135-N, 110-2 through 110-N, 111-2 through 111-N) in the one or more capacitor arrays which control the closed loop gain of the operational amplifier of the AGC circuit of this invention.

Abstract: A switched capacitor gain stage (110, 120) having a programmable gain factor. This gain factor is determined by the connection of desired gain determining components (14-17; 25-28) contained within a component array (100, 101). A sample and hold circuit (46) is provided for the storage of the error voltage of the entire gain-integrator stage. This stored error voltage (V.sub.error) is inverted and integrated one time for each integration of the input voltage (V.sub.in), thus eliminating the effects of the inherent offset voltages of the circuit from the output voltage (V.sub.out).

Abstract: A digital to analog converter (100) utilizes a current mirror connected to a reference voltage (V.sub.REF) to generate a constant reference current (I.sub.REF). A voltage divider (R.sub.1 and R.sub.2) is used in conjunction with a plurality of MOS transistors (X.sub.1 -X.sub.N) serving as current mirrors having specific current carrying capabilities which are controlled by selected binary digits (bits) of a digital signal. By the appropriate connection of desired ones of said plurality of MOS transistors, a specific fraction of said reference current is caused to flow through said plurality of MOS transistors. The amount of current flowing through said plurality of MOS transistors generates an output voltage (V.sub.OUT) from the digital to analog converter of this invention. This output voltage may be positive or negative with respect to the reference voltage, thus the output voltage is bipolar.

Abstract: A unique dynamic operational amplifier is constructed utilizing a switched capacitor (25) as the biasing means, wherein the switched capacitor biasing means is capable of effectively doubling the power supply voltage supplied to the dynamic operational amplifier, thus greatly extending the range of the input voltage (V.sub.IN) and output voltage (V.sub.OUT) of the dynamic operational amplifier.

Abstract: An operational amplifier gain stage utilizing switched capacitor resistor equivalent circuits is designed utilizing a delayed clock reference signal (.phi..sub.D, .phi..sub.D) in a unique manner, thereby eliminating the effects of spurious error voltages (E.sub.S) generated when utilizing metal oxide silicon field effect transistors as switches (12, 15, 21, 23, 25). The single remaining MOSFET switch (21) which will contribute a spurious voltage component to the output of the operational amplifier gain stage is designed in such a manner as to minimize the spurious voltage generated during operation of the MOSFET switch. A single dummy switch (31) is utilized to further minimize the spurious voltage generated by this single MOSFET switch.

Abstract: In an analog to digital converter circuit for a CODEC a single reference voltage is used for comparing both positive and negative input signals. The circuit comprises a capacitor array to define the decision levels corresponding to the end points of companding elements with the top plates of all capacitors in the array being connected in parallel through a single switch from an incoming analog signal source and to one input of a comparator. The bottom plate of each capacitor is connected to one of a series of three-way switches, all of which have separate terminals connected to the output of a voltage reference, to separate switches on a linear resistor string connected to the voltage reference output, and to ground. All switches are controlled by control logic connected to the comparator output.

Abstract: An integrator circuit utilizing an operational amplifier and switched capacitor elements in place of resistors in such a manner as to provide compensation for voltage offsets present in the operational amplifier resulting in an output voltage free from the effects of voltage offsets inherent in operational amplifiers.

Abstract: An autozero loop for eliminating offsets in the analog to digital converter section of a voice frequency coder-decoder (CODEC) utilizing an array of capacitors and a linear resistor string. The autozero loop functions with a relatively small time constant to null offsets quickly during the power-up phase of CODEC operation and with a higher time constant after the power-up phase. A dual bandwidth sub-circuit in the loop is connected to a voltage generator and controlled by signals from a logic circuit to operate at different bandwidths and thus provide different offset cancelling feedback signals during the power-up and normal operating phases.

Abstract: An operational amplifier (10a) comprised of MOSFET elements is disclosed which provides for a variable drive for an output stage that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section (14) comprised of complementary MOS elements (24, 26) is connected to a single MOSFET (40) that furnishes constant current to the signal input section of a differential amplifier section (20). The output of this differential amplifier is furnished by one path (70) directly to one complementary MOSFET element (72) of an output stage (18) and by another path (114) to a level shift section (16) which provides an output to a second complementary MOSFET element (80) of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain.

Abstract: An operational amplifier is designed to eliminate the effects of inherent voltage affects when used as a voltage comparator, while maintaining a high slew rate and a fast response time by providing a feedback capacitor which can be connected and disconnected between the output terminal and the noninverting current mirror input leg.

Abstract: An operational amplifier circuit comprised of complementary MOS transistors and having a bias section, a differential amplifier section, a level shift stage and an output stage, provides for frequency compensation using two capacitors. One capacitor, connected between the differential amplifier section and the output stage through a CMOS transmission gate that functions as a resistor, acts as the dominant pole of the transfer function. A second capacitor between the amplifier section output node and a level shift transistor, functions to remove the secondary poles in the transfer function and cause the dominant pole to occur at a higher frequency.

Abstract: An operational amplifier of MOSFET elements is disclosed which provides for a variable drive for an output stage that results in lower power dissipation and increased gain factor over comparable circuits using constant bias drive for the output stage. A bias section comprised of complementary MOS elements is connected to a single MOSFET that furnishes constant current to the signal input section of a differential amplifier section. The output of this differential amplifier is furnished by one path directly to one complementary MOSFET element of a high impedance output stage and by another path to a level shift section which provides an output to a second complementary MOSFET element of the output stage. Thus, the circuit functions under class A-B operation at low power dissipation and provides high open loop gain. Additional embodiments of the invention utilize three MOSFET elements in the level shift section or an additional output stage having an NPN transistor in combination with an N-channel MOSFET.