Abstract: The display device of this invention has two types of DA converter for converting a digital image signal to an analog image signal; a first DA converter disposed in the peripheral area of a plurality of pixel elements and a second DA converter disposed within each of the pixel elements. The first DA converter converts the upper four-bit of a six-bit digital image signal and the second DA converter converts the remaining lower two-bit. This enables the simplification of the peripheral circuits of the pixel element, preventing size increase of the framing area of the display panel, while achieving the multiple-depth display with an increased number of the bits of the DA converter. In the display device with the built-in DA converter, the multiple-bit can be achieved while preventing the increase in the circuit size.

Abstract: The display device of this invention has a pixel element electrode 80, a plurality of drain signal lines 61 for supplying the digital image signals D0- D2, a plurality of capacitance elements C0-C2 with weighed capacitance value corresponding to the digital image signals D0-D2, a refresh transistor RT for initializing the voltage of the pixel element electrode 80 to the voltage Vsc, and charge transfer transistors TT0-TT2 for supplying the charge accumulated in the capacitance elements C0-C2 to the pixel element electrode 80. An image is displayed by supplying the analog image signal corresponding to the digital image signals D0-D2 to the pixel element electrode 80. The configuration of the peripheral circuits of the pixel element portion is simplified, leading to the reduction of the framing area of the panel.

Abstract: A display device has a power line providing a retaining circuit with a power voltage, which is also used as a storage capacitance line connected to one of the electrodes of a storage capacitor. The storage capacitance line is disposed parallel to gate signal lines in a pixel element of the device. The power line of two inverter circuits, which form the retaining circuit, extends in the direction perpendicular to the storage capacitance line and is connected to the storage capacitance line. This configuration helps to reduce the overall size of the display device.

Abstract: In the active matrix display device with a DRAM as the retaining circuit, the voltage retained in the retaining circuit is set in the brightness saturation region, which is outside the region of the voltage used in the moving picture display mode. With the voltage in this region, the difference in the brightness will not be recognized even if the voltage decreases before the refreshing operation. This prevents flickering and improves the display quality.

Abstract: In a display device, under a analog display mode, an analog image signal amplified by an analog amplifier is outputted to a liquid crystal display panel. Under an digital display mode, after being processed by a signal processing circuit, the digital image signal is outputted to the liquid crystal display panel through a DA converter and an amplifier. For writing a “white” image signal, the signal processing circuit converts the input digital signal so that all bits of the signal are a “1.” Also, for writing a “black” image signal, the signal processing circuit converts the input digital signal so that all bits of the signal are a “0.

Abstract: A display device, under a digital display mode, performs writing of digital image signals into a static memory circuit while a power voltage of about 3V is applied to the static memory with a panel drive frequency reduced from 60 Hz to 20-30 Hz. It is thus possible to output the digital image signal from a frame memory directly to a liquid crystal display panel without using a level shifter.

Abstract: A display device has a drain drive circuit, to which a horizontal output enable signal is applied in synchronization with a horizontal scanning signal. The enable signal allows the horizontal scanning signal to be supplied only to the gates of selected sampling transistors. Gate signal lines are also selected by a gate drive circuit. Accordingly, any set of arbitrary pixel elements in the display device are selected for rewriting the signal retained in the pixel elements.

Abstract: The active matrix display device of this invention operates under two operation modes: a normal operation mode in which the pixel element electrode sequentially receives the pixel element voltage in response to an image signal sequentially inputted and a memory operation mode in which display is made based on the data held by the retaining circuit. In this active matrix display device, at least a part of the retaining circuit is set for the predetermined voltage and functions as a storage capacitance element for holding the voltage between the pixel element electrode and the common electrode under the normal operation mode. In this configuration, it is possible to reduce the size of the storage capacitance element originally disposed, because at least a part of the retaining circuit works as the storage capacitance element. Therefore, as the size of the storage capacitance element gets smaller, the size of the pixel element can also be smaller, leading to the size reduction of the device as a whole.

Abstract: The supply voltage to a driving circuit (100) and LCD (200) generated by a power supply circuit (350) is controlled to be periodically turned on and off during a power save mode, using a timer circuit (260) or timer such as a counting circuit. In this manner, during the power save mode, the power consumption can be reduced by turning off the power supply, and, at the same time, the display can be periodically shown without any further manipulation. By suspending the output of the gate selection signals to the display panels before the control to turn off the power supply, the display immediately before the turn off operation can be maintained even after the power supply is turned off.

Abstract: The switching between the normal operation mode and the memory operation mode is achieved by disposing one retaining circuit 110 for a plurality of pixel elements (for example, 2 or 4 pixel elements). The retaining circuit 110, which is a SRAM, requires considerable circuit space. The sharing of one retaining circuit by a plurality of the pixel elements enables the reduction of the seeming “number of the pixel elements” under the memory operation mode. This can lead to the size reduction of the pixel element, achieving the finer display under the normal operation mode. Also, the reduction in the number of the retaining circuits can further reduce the energy consumption under the memory operation mode, comparing to the case where the retaining circuit 110 is disposed for each of the pixel elements.

Abstract: A liquid crystal display apparatus includes a liquid crystal display panel having preset display characteristics, such as image brightness and contrast. A luminescent unit is optically connected with the display panel and provides light to the display panel in order to form an image on the display panel. The luminescent unit includes a light collector which collects ambient light and a light source, for generating light when the amount of ambient light is insufficient to generate a clear image. A control circuit is electrically connected to the display panel and automatically varies the preset display characteristics in accordance with the amount of ambient light collected by the light collector.

Abstract: There is provided a display device which enables both a full color moving image display (analog mode) and a shallow depth still image display (digital mode), and which achieves a significant reduction in the energy consumption of the display device system including the external LSI. Each of the pixel elements of the display device has two different display circuits corresponding to the respective display modes and a switching circuit for selecting one of them. When the digital mode is selected, the supply of the voltage power to the circuits not required to operate (a DA converter, a operational amplifier and a timing controller) under the mode is halted for reducing the consumption of the electric power by the display device.

Abstract: In the driving of a liquid crystal display panel with pixels in a matrix comprising n rows and m columns, when a partial display instruction is issued, respective rows in a display area (202) of s rows and m columns within the matrix are sequentially selected for one frame. Then, predetermined partial display data is written into the selected rows. Predetermined background data such as white display data is written into the background area (204) other than the partial display area (202). In the background area 204, either k rows and m columns or pixels of (the leading row ((s+1)-th row) of the background area, next to the final row in the partial display area) are selected during one frame for writing of the background display data, k rows and m columns are sequentially shifted each frame.

Abstract: A signal driving circuit for an active matrix type display device having display pixels arranged in a matrix, comprises a signal waveform correcting circuit receiving an input pixel signal for generating a corrected output pixel signal to the display device, said signal waveform correcting circuit including a delay circuit for generating a delay signal, a difference calculating circuit for calculating a difference signal between the input pixel signal and the delay signal, and a correction circuit for generating the corrected output pixel signal based upon the difference signal and the input pixel signal, wherein a portion of the waveform amplitude of the corrected output pixel signal is formed by adjusting a corresponding portion of the waveform amplitude of the input pixel signal based upon the difference signal.

Abstract: A power supply circuit (300) for a display device such as a liquid crystal outputs a boosted supply voltage VDD2 during normal operation, and generates a non-boosted supply voltage VDD2 having a voltage lower than that during the normal display operation by controlling the switches for switching the output within the power supply circuit (300) during a power save mode. The non-boosted supply voltage is supplied to the analog circuits of a driving circuit (100) so that the power consumption at the analog circuits is reduced. By controlling the switch for switching the output within the power supply circuit and the supply of the power supply clock, the circuit can be switched, in the power save mode, to either a mode where a lower supply voltage is generated or to a mode where the power supply is turned off.

Abstract: A driving circuit of a display device such as a liquid crystal generates power supply clocks (1 and 2) based on a system clock during the normal display operation which is not a power save mode. The generated power supply clocks are supplied, directly or after inversion, to the switches (SW1 through SW4 (and SW5 through SW8)) in a charge pump type power supply circuit (300) for switching the connection of capacitors (C1 and C2 (and C11 and C12)) in the power supply circuit (300). In this manner, supply voltages VDD2 and VDD3 which function as the driving power supply for a driving circuit (100) and a display panel (200) can be obtained at the power supply circuit (300) by boosting the input voltage Vin.

Abstract: In the &ggr; correction circuit, a crossover point arithmetic processing unit performs arithmetic processing for each region on crossover points y in the output data direction of a &ggr; correction crossover line based on a plurality of slope data A respectively specified for each of a plurality of regions and crossover point positions X in the input data direction set in advance.

Abstract: There is proposed is a method of controlling a flat panel display apparatus for multi-gradation display in which a data determination portion and a subfield control portion are provided. Based on a most significant bit or an upper bit of original image data, it is determined in which one of two or more divided gradation groups the original image data is included, to select a combination of subfields in accordance with a gradation-brightness characteristic of the belonging gradation group. Using a complementary relationship with human visibility, a difference in brightness between the gradations in a low-order brightness region is reduced, and a difference in brightness between the gradations in a high-order brightness region is enlarged. Therefore, a density of brightness is uniformly recognized visually over all the brightness regions, and a good quality of display can be obtained.

Abstract: An image processing apparatus detects, in step 1, whether or not differences between currently supplied image data and image data of a previous pixel are more than a predetermined value m, and identifies a border of a computer-created image or a natural image, where a brightness level differs from the remaining area of the image, when the differences are more than the predetermined value m. Conversely, when the differences are less than the predetermined value m, the image processing apparatus checks, in step 2, whether image data at a pixel before and a pixel two before the current pixel are identical with respect to the color components constituting the color image. When the differences are not all zero, it is checked whether or not the image data at a pixel before the current pixel and the image data at the current pixel are all zero. When the image data are not identical, the color image is identified as being a natural image.