Patents by Inventor Yutaka Ishibashi

Yutaka Ishibashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6303429
    Abstract: Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: October 16, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishibashi, Yusuke Kohyama, Tohru Ozaki
  • Patent number: 6153510
    Abstract: In a semiconductor device constituted using a borderless contact technique, for example, when a wiring layer with a damascene structure is connected to its underlying contact portion, a trench connect g with the contact portion is formed in the second interlayer insulation film. After that, the contact portion protruded from the bottom of the trench is selectively etched to flatten the bottom of the trench to remove a very small recess from that bottom of the trench which corresponds to a contact face between the contact portion and wiring layer. Thus, both a barrier metal layer and a metal layer for forming the wiring layer can be formed in the trench with higher reliability and accordingly the wiring layer and contact portion can be brought into reliable contact with each other. In a DRAM using a simple stacked capacitor, the storage electrode and plug portion can be put into reliable contact with each other.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Ishibashi
  • Patent number: 6150690
    Abstract: Capacitors are formed in the trenches made in an interlayer insulator made of silicon oxide. An insulating film (e.g., a silicon nitride film) is provided on the sides of each trench of the interlayer insulator. A storage electrode made of ruthenium or the like is provided in each trench of the interlayer insulator. A capacitor insulating film made of BSTO or the like is formed on the storage electrode. A plate electrode made of ruthenium or the like is formed on the capacitor insulating film. The plate electrode is common to all capacitors provided. Any two adjacent capacitors are electrically isolated by the interlayer insulator and the insulating film provided on the sides of the trenches of the interlayer insulator.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 21, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Ishibashi, Yusuke Kohyama, Toru Ozaki
  • Patent number: 5973348
    Abstract: In a semiconductor device constituted using a borderless contact technique, for example, when a wiring layer with a damascene structure is connected to its underlying contact portion, a trench connecting with the contact portion is formed in the second interlayer insulation film. After that, the contact portion protruded from the bottom of the trench is selectively etched to flatten the bottom of the trench to remove a very small recess from that bottom of the trench which corresponds to a contact face between the contact portion and wiring layer. Thus, both a barrier metal layer and a metal layer for forming the wiring layer can be formed in the trench with higher reliability and accordingly the wiring layer and contact portion can be brought into reliable contact with each other. In a DRAM using a simple stacked capacitor, the storage electrode and plug portion can be put into reliable contact with each other.
    Type: Grant
    Filed: February 12, 1998
    Date of Patent: October 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Ishibashi
  • Patent number: 5698869
    Abstract: A structure of a semiconductor device and a method of manufacturing the same is provided wherein a leakage current can be reduced while improving a drain breakdown voltage of an Insulated-Gate transistor such as a MOSFET, MOSSIT and a MISFET, and a holding characteristic of a memory cell such as a DRAM using these transistors as switching transistors can be improved, and further a reliability of a gate oxide film in a transfer gate can be improved. More particularly, a narrow band gap semiconductor region such as Si.sub.x Ge.sub.1-x, Si.sub.x Sn.sub.1-x, PbS is formed in an interior of a source region or a drain region in the SOI.IG-device. By selecting location and/or mole fraction of the narrow band gap semiconductor region in a SOI film, or selecting a kind of impurity element to compensate the crystal lattice mismatching due to the narrow-bandgap semiconductor region, the generation of crystal defects can be suppressed.
    Type: Grant
    Filed: September 13, 1995
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Yoshimi, Satoshi Inaba, Atsushi Murakoshi, Mamoru Terauchi, Naoyuki Shigyo, Yoshiaki Matsushita, Masami Aoki, Takeshi Hamamoto, Yutaka Ishibashi, Tohru Ozaki, Hitomi Kawaguchiya, Kazuya Matsuzawa, Osamu Arisumi, Akira Nishiyama
  • Patent number: 5689298
    Abstract: A multiple readout of digital video data, capable of realizing the fast forward and fast reverse modes even under the logically multiplexed circumstances, and reducing a time required for the playback mode switching. A cycle for a readout operation is formed by a plurality of slots, each slot representing a unit time for reading a unit amount of the digital video data for each channel assigned to each user terminal; at least one of the plurality of slots forming each cycle is allocated to each channel and at least one of the plurality of slots not yet used for any channel in each cycle is additionally allocated to a user terminal which is requesting a playback mode switching; and the readout operation to read the digital video data for each channel from the storage device is carried out at every slot allocated to each channel in each cycle, by cyclically repeating the cycle for the readout operation. The requested playback mode switching can be a switching to a fast forward/reverse mode.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: November 18, 1997
    Assignee: Nippon Telegraph & Telephone Corporation
    Inventors: Kazutoshi Nishimura, Yutaka Ishibashi, Tatsuo Mori
  • Patent number: 5672891
    Abstract: A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode.
    Type: Grant
    Filed: April 26, 1996
    Date of Patent: September 30, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Hamamoto, Takashi Yamada, Yutaka Ishibashi
  • Patent number: 5548145
    Abstract: A semiconductor memory device comprises a semiconductor substrate having memory cell area, a plurality of trenches selectively formed in the memory cell area aligning in certain intervals and a plurality of memory cell arrays provided in the memory cell area, wherein each of the memory cell arrays comprises a plurality of MOS transistors connected in a serial array and a plurality of capacitors each formed in a corresponding one of the trenches. Each of the transistors has a gate electrode above the substrate with a gate insulating film formed therebetween and source and drain regions formed in the substrate on both sides of the gate electrode.
    Type: Grant
    Filed: October 25, 1994
    Date of Patent: August 20, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takeshi Hamamoto, Takashi Yamada, Yutaka Ishibashi
  • Patent number: 5479303
    Abstract: A visual search control of digital video files capable of realizing a high quality image even in the fast forward and fast reverse modes, while facilitating a quick mode switching among the normal playback mode and the fast forward and fast reverse modes.
    Type: Grant
    Filed: October 20, 1993
    Date of Patent: December 26, 1995
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Hideharu Suzuki, Yutaka Ishibashi, Kazutoshi Nishimura
  • Patent number: 5386670
    Abstract: A floor panel having a rectangular floor base integrally with a convex prop in each corner portion and a concave portion on the upper surface of each prop. There is a height adjusting screw with a plate embedded in the concave portion of each prop, variably for adjusting the height of the support position in a predetermined range between a position lower than the upper surface of the prop and a position higher than the upper surface of the prop. A floor panel is supported by each prop of the floor base and has through holes for accessing the height adjusting screw for adjusting the support height at each corner according to the prop. In the method of manufacturing the floor base, a convex portion, which integrally projects to the upper surface side on four corners of a skin, is formed, a concave portion is formed on the lower surface of said convex portion, concrete is packed in the concave portion, thereby forming which is integral to said skin.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: February 7, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Yutaka Ishibashi, Isako Tsushima, Kenji Sugimoto, Hideo Tanaka, Hidetoshi Takahashi, Fumio Sumiyoshi
  • Patent number: 5245805
    Abstract: This invention relates to an interior panel unit having a structure in which a plurality of rectangular floor base members to be installed on a foundation floor of a room are connected to each other by base joint members. A plurality of fundamental support members having the same height and a plurality of connecting support members having the same height as that of the fundamental support members are located on each floor base member. Each floor panel member supported by the fundamental support members and the connecting support members is arranged to assure a predetermined space with the corresponding floor base member. Cables and various types of equipment which constitute an office-automation system are mounted in the space defined by the floor panel member and the floor base member. The space defined by the floor panel member and the floor base member is partitioned by vertical and horizontal separator members. The cables and various types of equipment are appropriately arranged in the partitioned space.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: September 21, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Tsuneo Kaneko, Yutaka Ishibashi, Naoto Sasaki, Isako Tsushima
  • Patent number: 5197244
    Abstract: This invention relates to an interior panel unit having a structure in which a plurality of rectangular floor base members to be installed on a foundation floor of a room are connected to each other by base joint members. A plurality of fundamental support members having the same height and plurality of connecting support members having the same height as that of the fundamental support members are located on each floor base member. Each floor panel member supported by the fundamental support members and the connecting support members is arranged to assure a predetermined space with the corresponding floor base member. Cables and various types of equipment which constitute an office-automation system are mounted in the space defined by the floor panel member and the floor base member. The space defined by the floor panel member and the floor base member is partitioned by vertical and horizontal separator members. The cables and various types of equipment are appropriately arranged in the partitioned space.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: March 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Tsuneo Kaneko, Yutaka Ishibashi, Naoto Sasaki, Isako Tsushima
  • Patent number: 5187907
    Abstract: This invention relates to an interior panel unit having a structure in which a plurality of rectangular floor base members to be installed on a foundation floor of a room are connected to each other by base joint members. A plurality of fundamental support members having the same height and a plurality of connecting support members having the same height as that of the fundamental support members are located on each floor base member. Each floor panel member supported by the fundamental support members and the connecting support members is arranged to assure a predetermined space with the corresponding floor base member. Cables and various types of equipment which constitute an office-automation system are mounted in the space defined by the floor panel member and the floor base member. The space defined by the floor panel member and the floor base member is partitioned by vertical and horizontal separator members. The cables and various types of equipment are appropriately arranged in the partitioned space.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: February 23, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Tsuneo Kaneko, Yutaka Ishibashi, Naoto Sasaki, Isako Tsushima
  • Patent number: 5184438
    Abstract: This invention relates to an interior panel unit having a structure in which a plurality of rectangular floor base members to be installed on a foundation floor of a room are connected to each other by base joint members. A plurality of fundamental support members having the same height and a plurality of connecting support members having the same height as that of the fundamental support members are located on each floor base member. Each floor panel member supported by the fundamental support members and the connecting support members is arranged to assure a predetermined space with the corresponding floor base member. Cables and various types of equipment which constitute an office-automation system are mounted in the space defined by the floor panel member and the floor base member. The space defined by the floor panel member and the floor base member is partitioned by vertical and horizontal separator members. The cables and various types of equipment are appropriately arranged in the partitioned space.
    Type: Grant
    Filed: October 11, 1991
    Date of Patent: February 9, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Tsuneo Kaneko, Yutaka Ishibashi, Naoto Sasaki, Isako Tsushima
  • Patent number: 5090169
    Abstract: This invention relates to an interior panel unit having a structure in which a plurality of rectangular floor base members to be installed on a foundation floor of a room are connected to each other by base joint members. A plurality of fundamental support members having the same height and a plurality of connecting support members having the same height as that of the fundamental support members are located on each floor base member. Each floor panel member supported by the fundamental support members and the connecting support members is arranged to assure a predetermined space with the corresponding floor base member. Cables and various types of equipment which constitute an office-automation system are mounted in the space defined by the floor panel member and the floor base member. The space defined by the floor panel member and the floor base member is partitioned by vertical and horizontal separator members. The cables and various types of equipment are appropriately arranged in the partitioned space.
    Type: Grant
    Filed: October 31, 1989
    Date of Patent: February 25, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumio Takeda, Yoshio Kojima, Tsuneo Kaneko, Yutaka Ishibashi, Naoto Sasaki, Isako Tsushima
  • Patent number: D337079
    Type: Grant
    Filed: August 2, 1991
    Date of Patent: July 6, 1993
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Harumi Okano, Yutaka Ishibashi
  • Patent number: D379945
    Type: Grant
    Filed: November 16, 1995
    Date of Patent: June 17, 1997
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Hiroyuki Kawase, Yutaka Ishibashi