Abstract: A laminated film containing a gas barrier layer and an inorganic polymer layer laminated on a resin substrate, wherein a Y value calculated from a transmission electron microscope image of a cross section of the inorganic polymer layer by the following procedures (a) to (d) is 0.220 or less: (a) Calculating a standard deviation (?) of the contrast of an electron beam-unirradiated part of the inorganic polymer layer; (b) Dividing an electron beam-irradiated part of the inorganic polymer layer into twenty parts having a film thickness equal in a film thickness direction, and calculating a standard deviation (an: standard deviation of nth division, n=1˜20) of the contrast of each divided part; (c) Calculating Xn (n=1˜20) of each divided part from the expression (1): Xn=?n/? (n=1˜20) . . . (1); and (d) A standard deviation of X3 to X18 is defined as Y.

Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.

Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: A driver including: an ejection part to which a fastener is supplied; a driver blade which moves from a first position toward a second position and drives the fastener into a driven member; and a rack provided to the driver blade. The driver further includes: a rotary component engaging with the rack and moving the driver blade from the second position to the first position; and a lock plate engaging with the rack. The driver blade moves from the second position to the first position while the rotary component rotates once, the rotary component is released from engaging with the rack after the driver blade moves from the second position to the first position, and moves from the first position to the second position, and the lock plate is engageable with the rack when the driver blade stops before reaching the second position from the first position.

Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.

Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh rate for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one internal auto refresh of the memory bank in response to the operating temperature being less than or equal to a first threshold temperature. A memory device and an electronic system are also described.

Abstract: Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Abstract: A driver including: an ejection part to which a fastener is supplied; a driver blade which moves from a first position toward a second position and drives the fastener into a driven member; and a rack provided to the driver blade. The driver further includes: a rotary component engaging with the rack and moving the driver blade from the second position to the first position; and a lock plate engaging with the rack. The driver blade moves from the second position to the first position while the rotary component rotates once, the rotary component is released from engaging with the rack after the driver blade moves from the second position to the first position, and moves from the first position to the second position, and the lock plate is engageable with the rack when the driver blade stops before reaching the second position from the first position.

Abstract: An apparatus may include an address counter to provide first address information and second address information. The first address information may include a first number of bits and the second address information may include a second number of bits that is smaller than the first number of bits. The address counter may perform a first updating operation. The first updating operation being such that the first address information is updated from a first initial value to a first final value. The address counter may also perform a second updating operation, the second updating operation being such that the second address information is updated from a second initial value to a second final value. In addition, the address counter may also perform the second updating operation at least twice per the first updating operation being performed once.

Abstract: A semiconductor device according to an aspect of the present invention has: a plurality of memory cells MC; a plurality of word lines WL each coupled to a corresponding one of the plurality of memory cells MC; and a control circuit that intermittently monitors accesses to the plurality of word lines WL, stores/erases some captured row-addresses in a first number of registers, and detects, by comparison with stored addresses, in response to a first number of accesses to one of the word lines WL in a first period of time. According to the present invention, access histories can be precisely analyzed by a small-scale circuit configuration, and measures against, for example, the Row Hammer problem, etc. can be taken.

Abstract: A liquid crystal display device is provided with a display substrate, an array substrate, a liquid crystal layer sandwiched between the display substrate and the array substrate, and control circuitry. The display substrate includes a touch sensing line. The array substrate includes a common electrode having a constant potential, a first insulating layer provided under the common electrode, a pixel electrode provided under the first insulating layer, a second insulating layer provided under the pixel electrode, a conductive line electrically connected to the common electrode under the second insulating layer, a third insulating layer provided under the conductive line, and a first active element and a second active element provided under the third insulating layer and electrically connected to the pixel electrode.

Abstract: An X-ray CT imaging apparatus includes: a supporter that is supported such that an X-ray generator and an X-ray detector are opposed to each other; a turning motor that turns the supporter about a shaft; a crosswise drive motor that moves the shaft in a crosswise direction; and a circuit that performs processing of controlling the turning motor and the crosswise drive motor and processing of setting the physique of a subject. When X-ray CT imaging is performed, the crosswise drive motor moves the shaft in synchronization with turning of the supporter about the shaft, and the supporter is caused to perform combined motion, which allows the X-ray generator and the X-ray detector to turn about a center of an X-ray CT imaging region, and position control of the shaft is performed according to the size of the physique of the subject.

Abstract: Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

Abstract: A display device for a medical X-ray photography apparatus may include: a display panel including a photography mode selection region where a plurality of photography mode selection images corresponding to a plurality of X-ray photography modes are displayed; an interface that receives a selection operation to select one of the photography mode selection images displayed on the display panel; a processor that performs display processing of the selected photography mode selection image displayed on the display panel in response to the selection operation received through the interface; and an illustration display region included in the display panel where an illustration corresponding to the selected photography mode selection image is displayed. When the selection operation is received, the selected photography mode selection image is displayed in a visually distinguishable manner, and the illustration corresponding to the selected photography mode is displayed in the illustration display region.

Abstract: Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.

Abstract: A laminated film includes a flexible base material, a first thin film layer formed on at least one of surfaces of the base material, and a second thin film layer formed on the first thin film layer, and the first thin film layer contains a silicon atom (Si), an oxygen atom (O) and a carbon atom (C), the second thin film layer contains a silicon atom, an oxygen atom and a nitrogen atom (N), and the first thin film layer and the second thin film layer are formed by using glow discharge plasma.

Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number.

Abstract: Apparatuses for executing interrupt refresh are described. An example apparatus includes: memory banks, a sampling timing generator circuit, bank sampling circuits and a command state signal generator circuit that provides a command state signal responsive to a command. Each memory bank includes a latch that stores an address for interrupt refresh. The sampling timing generator circuit receives an oscillation signal and provides a trigger signal of sampling the address. Each bank sampling circuit is associated with a corresponding memory bank. Each bank sampling circuit provides a sampling signal to the latch in the corresponding memory bank responsive to the trigger signal of sampling the address. The sampling timing generator circuit provides the trigger signal of sampling the address, responsive, at least in part, to the command state signal, and the latch stores the address, responsive, at least in part, to the at least one trigger signal of sampling the address.

Abstract: Techniques described herein are related to protecting at least a portion of data stored in a memory array. A method may include detecting an invalid memory access request based at least in part on the secret key and the identifier and preventing unauthorized access of a memory array by halting an internal refresh of one or more memory cells associated with the memory array in response to detecting the invalid memory access request.

Abstract: Apparatuses and methods for executing row hammer (RH) refresh are described. An example apparatus includes a RH control circuit to provide a row hammer address, and a refresh control circuit to perform a RH refresh operation on a memory address array related to the RH address. The RH control circuit includes first latches each to store an old row address used to access the memory and second latches provided correspondingly to the first latches each set to a state indicating whether the old row address stored in one of the first latches is valid. The RH control circuit further including a signal generator configured to assert a sample signal when a new row address to be used to access the memory array matches the old row address stored in any one of the first latches is valid based on a state of one of the second latches.