Patents by Inventor Yutaka Onozuka

Yutaka Onozuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160231265
    Abstract: According to one embodiment, an analysis package including an analysis chip provided on a main surface of a semiconductor substrate, the chip including a flow channel, both ends of which are open at peripheral parts of the substrate, and a microaperture which is provided in a middle of the flow channel and which allows a particle to pass therethrough, a package board on which the chip is mounted, liquid receivers provided on the package board, the liquid receivers being connected to openings, and electrodes, at least parts of which are provided on parts of bottom surfaces of the liquid receivers, the electrodes being provided at positions corresponding to an upstream side and a downstream side of the microaperture.
    Type: Application
    Filed: September 9, 2015
    Publication date: August 11, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi HAMASAKI, Michihiko NISHIGAKI, Yutaka ONOZUKA, Kentaro KOBAYASHI, Hiroko MIKI, Naofumi NAKAMURA
  • Patent number: 9397057
    Abstract: According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: July 19, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki
  • Publication number: 20160153935
    Abstract: According to one embodiment, a microanalysis chip includes a substrate, a flow channel in which a sample liquid is allowed to flow, the flow channel being provided on a main surface side of the substrate, a reservoir in which the sample liquid is allowed to be stored, the reservoir being provided on a main surface of the substrate, including a bank having a go-around shape and further including a liquid introduction inlet for connection to an end of the flow channel, the liquid introduction inlet being provided on the main surface of the substrate in the bank, and a filter which is provided between the liquid introduction inlet and the end of the flow channel and includes a first micropore for allowing passage of a fine particle in the sample liquid.
    Type: Application
    Filed: June 5, 2015
    Publication date: June 2, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Michihiko NISHIGAKI, Yutaka ONOZUKA, Kentaro KOBAYASHI, Hiroshi HAMASAKI, Naofumi NAKAMURA
  • Publication number: 20150348924
    Abstract: According to an embodiment, a semiconductor device comprises an insulative resin, an interconnect, a plurality of semiconductor elements, a first conductive unit, a first connector, and a first metal layer. The insulative resin includes a first region and a second region. At least a portion of the interconnect is arranged with at least a portion of the first region in a first direction. The first conductive unit pierces the second region in the first direction. At least a portion of the first connector is arranged with at least a portion of the first conductive unit in the first direction. At least a portion of the first connector is arranged with at least a portion of the interconnect in a second direction intersecting the first direction. The first metal layer is provided between the first conductive unit and the first connector. The first metal layer contacts the insulative resin.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 3, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Nobuto Managaki
  • Publication number: 20150348937
    Abstract: According to one embodiment, a semiconductor device includes an insulative resin, an interconnect, a plurality of semiconductor elements, and a first metal member. The insulative resin includes a first region and a second region. The interconnect is arranged with the first region in a first direction. The first direction intersects a direction from the first region toward the second region. The plurality of semiconductor elements is provided between the first region and the interconnect. At least one of the plurality of semiconductor elements is electrically connected to the interconnect. The first metal member includes a first through-portion and a first end portion. The first through-portion pierces the second region in the first direction. The first end portion is connected to the first through-portion. A width of the first end portion is wider than a width of the first through-portion in a second direction intersecting the first direction.
    Type: Application
    Filed: April 21, 2015
    Publication date: December 3, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yutaka ONOZUKA, Hiroshi YAMADA, Nobuto MANAGAKI
  • Publication number: 20150279802
    Abstract: A semiconductor device according to an embodiment includes a semiconductor chip, a cap disposed to face the semiconductor chip, and having a through-hole electrode arranged in a through hole, and a bump electrode provided between the semiconductor chip and the cap, wherein the bump electrode is in a protruding shape connecting the semiconductor chip and the through-hole electrode, and wherein at least a portion of the bump electrode is included in the through-hole electrode, and electrically connected thereto, so that the adhesive performance between the cap and the bump electrode can be increased.
    Type: Application
    Filed: March 9, 2015
    Publication date: October 1, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yutaka ONOZUKA, Hiroshi Yamada, Nobuto Managaki, Tadahiro Sasaki
  • Publication number: 20150201488
    Abstract: A wiring board of an embodiment includes a through via, a first insulating film disposed around the through via, a second insulating film disposed around the first insulating film, a third insulating film disposed around the second insulating film and a resin disposed around the third insulating film. The resin includes fillers. The second insulating film has a relative permittivity lower than a relative permittivity of the first insulating film. The third insulating film has a relative permittivity higher than a relative permittivity of the second insulating film.
    Type: Application
    Filed: December 30, 2014
    Publication date: July 16, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Nobuto MANAGAKI, Tadahiro SASAKI, Atsuko IIDA, Yutaka ONOZUKA, Hiroshi YAMADA
  • Publication number: 20150123275
    Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi YAMADA, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya
  • Publication number: 20150084208
    Abstract: A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal plane provided in the dielectric material, the first metal plane being perpendicular to an extension direction of the penetrating via, the first metal plane crossing the penetrating via, and a second metal plane provided n or on the dielectric material in parallel with the extension direction of the penetrating via, the second metal plane connected to the first metal plane.
    Type: Application
    Filed: August 22, 2014
    Publication date: March 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsuko IIDA, Tadahiro Sasaki, Nobuto Managaki, Yutaka Onozuka, Hiroshi Yamada
  • Patent number: 8980697
    Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: March 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya
  • Patent number: 8951905
    Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Kazuhiko Itaya
  • Publication number: 20150021748
    Abstract: A semiconductor device of an embodiment includes: a substrate, a high-frequency integrated circuit being provided on the substrate, a cap, and a sealing wall provided between the substrate and the cap. The cap includes a first conductive layer, a second conductive layer, an insulating layer provided between the first conductive layer and the second conductive layer, and a conductive via provided in the insulating layer. The conductive via connects the first conductive layer and the second conductive layer. The first conductive layer or the second conductive layer is connected to a ground potential. The sealing wall surrounds the high-frequency integrated circuit.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 22, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro SASAKI, Kazuhiko Itaya, Hiroshi Yamada, Yutaka Onozuka, Nobuto Managaki
  • Publication number: 20150022416
    Abstract: An antenna device of the present embodiment includes: a first conductive layer connected to a ground potential, a semiconductor device provided above the first conductive layer, a second conductive layer provided above the semiconductor device, a first via connecting the second conductive layer and the first conductive layer, a third conductive layer provided above the second conductive layer, a second via passing through the first opening, and an antenna provided above the third conductive layer. A dielectric is provided between the second conductive layer and the semiconductor device, between the third conductive layer and the second conductive layer, and between the antenna and the third conductive layer. The second conductive layer includes a first opening. The second via connects the third conductive layer and the first conductive layer.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 22, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro SASAKI, Kazuhiko ITAYA, Hiroshi YAMADA, Yutaka ONOZUKA, Nobuto Managaki, Atsuko IIDA
  • Publication number: 20140091447
    Abstract: A semiconductor device according to an embodiment includes: a first unit device configured to include a semiconductor chip, a backside electrode that is in contact with a backside of the semiconductor chip, and a bonding wire in which one end is connected to the backside electrode; a second unit device configured to have a function different from that of the first unit device; a resin layer configured to fix the first and second unit devices to each other; and a first wiring that is formed on the resin layer on a surface side of the semiconductor chip and connected to the other end of the bonding wire.
    Type: Application
    Filed: September 11, 2013
    Publication date: April 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yutaka ONOZUKA, Hiroshi Yamada, Kazuhiko Itaya
  • Publication number: 20130234308
    Abstract: A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
    Type: Application
    Filed: February 13, 2013
    Publication date: September 12, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Yutaka Onozuka, Atsuko Iida, Kazuhiko Itaya
  • Patent number: 8008760
    Abstract: An integrated semiconductor device includes a plurality of semiconductor elements having different integrated element circuits or different sizes; an insulating material arranged between the semiconductor elements; an organic insulating film arranged entirely on the semiconductor elements and the insulating material; a fine thin-layer wiring that arranged on the organic insulating film and connects the semiconductor elements; a first input/output electrode arranged on an area of the insulating material; and a first bump electrode formed on the first input/output electrode.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 30, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Yamada, Kazuhiko Itaya, Yutaka Onozuka, Hideyuki Funaki
  • Patent number: 7906823
    Abstract: A MEMS apparatus includes a MEMS unit formed on a semiconductor substrate and a cover provided with a pore and serving to seal the MEMS unit. The pore is sealed with a sealing material shaped in a sphere or a hemisphere.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Suzuki, Michihiko Nishigaki, Yutaka Onozuka, Hiroshi Yamada, Kazuhiko Itaya, Hideyuki Funaki
  • Patent number: 7893525
    Abstract: It is made possible to restrict warpage at the time of resin cure and achieve a smaller thickness. A semiconductor device includes: a first chip including a MEMS device and a first pad formed on an upper face of the MEMS device, the first pad being electrically connected to the MEMS device; a second chip including a semiconductor device and a second pad formed on an upper face of the semiconductor device, the second pad being electrically connected to the semiconductor device; and an adhesive portion having a stacked structure, and bonding a side face of the first chip and a side face of the second chip, the stacked structure including a first adhesive film formed by adding a first material constant modifier to a first resin, and a second adhesive film formed by adding a second material constant modifier to a second resin.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: February 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Iida, Yutaka Onozuka, Kazuhiko Itaya
  • Patent number: 7875481
    Abstract: It is made possible to provide a highly integrated, thin apparatus can be obtained, even if the apparatus contains MEMS devices and semiconductor devices. A semiconductor apparatus includes: a first chip comprising a MEMS device formed therein; a second chip comprising a semiconductor device formed therein; and an adhesive layer bonding a side face of the first chip to a side face of the second chip, and having a lower Young's modulus than the material of the first and second chips.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: January 25, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yutaka Onozuka, Hiroshi Yamada, Hideyuki Funaki, Kazuhiko Itaya
  • Patent number: 7863617
    Abstract: A method of manufacturing an active matrix type display device, which is reliable and flexible, is provided. An active matrix type display device according to an aspect of the present invention includes: a first substrate, which is flexible; a thin glass layer provided on the first substrate via an adhesion layer, and having projections and depressions on a surface thereof opposing to the first substrate, the projections and depressions having rounded tips and bottoms; active elements provided on the thin glass layer, each active element corresponding to a pixel; a display provided above the thin glass layer, and driven by the active elements to display an image pixel by pixel; and a second substrate provided on the display, and having an opposing electrode formed thereon.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsuyoshi Hioki, Masahiko Akiyama, Mitsuo Nakajima, Yujiro Hara, Yutaka Onozuka