Patents by Inventor Yutaka Shionoiri

Yutaka Shionoiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9448432
    Abstract: It is an object to provide a display having high visibility and a transflective type liquid crystal display device having a reflection electrode having a concavo-convex structure formed without especially increasing the process. During manufacturing a transflective liquid crystal display device, a reflection electrode of a plurality of irregularly arranged island-like patterns and a transparent electrode of a transparent conductive film are layered in forming an electrode having transparent and reflection electrodes thereby having a concavo-convex form to enhance the scattering ability of light and hence the visibility of display. Furthermore, because the plurality of irregularly arranged island-like patterns can be formed simultaneous with an interconnection, a concavo-convex structure can be formed during the manufacturing process without especially increasing the patterning process only for forming a concavo-convex structure. It is accordingly possible to greatly reduce cost and improve productivity.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: September 20, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Shingo Eguchi, Yutaka Shionoiri, Etsuko Fujimoto
  • Patent number: 9425215
    Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: August 23, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kiyoshi Kato, Jun Koyama, Yutaka Shionoiri
  • Publication number: 20160217761
    Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
    Type: Application
    Filed: November 16, 2015
    Publication date: July 28, 2016
    Inventors: Hajime Kimura, Yutaka Shionoiri
  • Publication number: 20160203871
    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
    Type: Application
    Filed: January 8, 2016
    Publication date: July 14, 2016
    Inventors: Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Takanori Matsuzaki, Yutaka Shionoiri, Kiyoshi Kato
  • Patent number: 9391674
    Abstract: To provide a power feeding system and the like with which charging can be performed without a decrease in the power supply efficiency. To provide a power feeding system and the like with which can offer a power feeding service which is efficient to both a power feeding user and a power feeding provider. The power transmission state in each of power transmitting portions is monitored, the power transmitting portion having the highest power transmission efficiency is selected based on positional advantage, and the power transmitting resonance coil included in the selected power transmitting portion is kept at a first resonance frequency, whereby power transmission continues. The resonance frequency of the power transmitting resonance coil included in the non-selected power transmitting portion (the number of the non-selected power transmitting portions may be plural) is set to a second resonance frequency, whereby power transmission is stopped.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: July 12, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Misako Miwa, Koichiro Kamata, Yutaka Shionoiri, Shuhei Maeda
  • Publication number: 20160187946
    Abstract: Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.
    Type: Application
    Filed: March 3, 2016
    Publication date: June 30, 2016
    Inventors: Misako MIWA, Yutaka SHIONOIRI
  • Patent number: 9343120
    Abstract: A semiconductor device in which the power consumption of a register is low is provided. Further, a processing unit whose operation speed is high and whose power consumption is low is provided. In the semiconductor device, a register operating at high speed and a nonvolatile FILO (first-in-last-out) register capable of reading and writing data from/to the register are provided.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: May 17, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi, Yoshiyuki Kurokawa
  • Patent number: 9336850
    Abstract: The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 10, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Hidetomo Kobayashi
  • Publication number: 20160094236
    Abstract: An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.
    Type: Application
    Filed: September 23, 2015
    Publication date: March 31, 2016
    Inventors: Yutaka SHIONOIRI, Kiyoshi KATO, Tomoaki ATSUMI
  • Patent number: 9285848
    Abstract: Provided is a power reception device in which power consumption at the time of wireless power supply is reduced. A power reception device is provided with a power reception control device capable of temporarily stopping supply of power supply voltage to a communication control unit for controlling communication in a break period of communication intermittently performed between a power transmission device and a power reception device. In the structure, a clock signal is generated on the basis of a power receiving signal transmitted from the power transmission device, and a period of communication intermittently performed can be measured using the clock signal. Further, a structure may be employed in which supply of power supply voltage to the communication unit in the power reception control device can be stopped in the break period of the communication.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: March 15, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Misako Miwa, Yutaka Shionoiri
  • Patent number: 9240244
    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: January 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Takanori Matsuzaki, Yutaka Shionoiri, Kiyoshi Kato
  • Publication number: 20150349131
    Abstract: A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 3, 2015
    Inventors: Tomoaki ATSUMI, Yoshiyuki KOBAYASHI, Yutaka SHIONOIRI, Yuto YAKUBO, Shuhei NAGATSUKA, Shunpei YAMAZAKI
  • Publication number: 20150340379
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Application
    Filed: August 3, 2015
    Publication date: November 26, 2015
    Inventors: Yoshinori IEDA, Atsuo ISOBE, Yutaka SHIONOIRI, Tomoaki ATSUMI
  • Patent number: 9190425
    Abstract: A semiconductor device having a normal function means is provided, in which the amplitude of an output signal is prevented from being decreased even when a digital circuit using transistors having one conductivity is employed. By turning OFF a diode-connected transistor 101, the gate terminal of a first transistor 102 is brought into a floating state. At this time, the first transistor 102 is ON and its gate-source voltage is stored in a capacitor. Then, when a potential at the source terminal of the first transistor 102 is increased, a potential at the gate terminal of the first transistor 102 is increased as well by bootstrap effect. As a result, the amplitude of an output signal is prevented from being decreased.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: November 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yutaka Shionoiri
  • Publication number: 20150325599
    Abstract: The invention provides a processor obtained by forming a high functional integrated circuit using a polycrystalline semiconductor over a substrate which is sensitive to heat, such as a plastic substrate or a plastic film substrate. Moreover, the invention provides a wireless processor, a wireless memory, and an information processing system thereof which transmit and receive power or signals wirelessly. According to the invention, an information processing system includes an element forming region including a transistor which has at least a channel forming region formed of a semiconductor film separated into islands with a thickness of 10 to 200 nm, and an antenna. The transistor is fixed on a flexible substrate. The wireless processor in which a high functional integrated circuit including the element forming region is formed and the semiconductor device transmit and receive data through the antenna.
    Type: Application
    Filed: July 17, 2015
    Publication date: November 12, 2015
    Inventors: Shunpei YAMAZAKI, Kiyoshi KATO, Jun KOYAMA, Yutaka SHIONOIRI
  • Patent number: 9171630
    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Takanori Matsuzaki, Yutaka Shionoiri, Kiyoshi Kato
  • Publication number: 20150301388
    Abstract: An object of the present invention is to provide a transflective liquid crystal display device having an excellent visibility obtained by optimizing the arrangement of a color filter, which would become a problem in the process of fabricating transparent and reflective liquid crystal display devices, for the transflective liquid crystal display device. In the present invention, the arrangement of a color filter is optimized for improving the visibility of the transflective liquid crystal display device. In addition, the structure, which allows the formation of color filters without increasing the capacitance that affects on a display, is fabricated. Furthermore, in the process of fabricating the transflective liquid crystal display device, an uneven structure is additionally formed without particularly increasing an additional patterning step for the formation of such an uneven structure.
    Type: Application
    Filed: June 8, 2015
    Publication date: October 22, 2015
    Inventors: Shingo Eguchi, Yutaka Shionoiri
  • Publication number: 20150294693
    Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 15, 2015
    Inventors: Tatsuya ONUKI, Kiyoshi KATO, Yutaka SHIONOIRI, Tomoaki ATSUMI, Takanori MATSUZAKI, Hiroki INOUE, Shuhei NAGATSUKA, Yuto YAKUBO
  • Patent number: 9154035
    Abstract: One object is to provide a boosting circuit whose boosting efficiency is enhanced. Another object is to provide an RFID tag including a boosting circuit whose boosting efficiency is enhanced. A node corresponding to an output terminal of a unit boosting circuit or a gate electrode of a transistor connected to the node is boosted by bootstrap operation, so that a decrease in potential which corresponds to substantially the same as the threshold potential of the transistor can be prevented and a decrease in output potential of the unit boosting circuit can be prevented.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yutaka Shionoiri, Junpei Sugao
  • Publication number: 20150263007
    Abstract: A semiconductor device with a transistor having favorable electrical characteristics is provided. The semiconductor device has a memory circuit and a circuit that are over the same substrate. The memory circuit includes a capacitor, a first transistor, and a second transistor. A gate of the first transistor is electrically connected to the capacitor and one of a source and a drain of the second transistor. The circuit includes a third transistor and a fourth transistor that are electrically connected to each other in series. The first transistor and the third transistor each include an active layer including silicon, and the second transistor and the fourth transistor each include an active layer including an oxide semiconductor.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 17, 2015
    Inventors: Shunpei YAMAZAKI, Yutaka SHIONOIRI, Tomoaki ATSUMI, Shuhei NAGATSUKA, Yutaka OKAZAKI, Suguru HONDO